CN108807308A - 封装结构及封装工艺方法 - Google Patents

封装结构及封装工艺方法 Download PDF

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Publication number
CN108807308A
CN108807308A CN201710749776.7A CN201710749776A CN108807308A CN 108807308 A CN108807308 A CN 108807308A CN 201710749776 A CN201710749776 A CN 201710749776A CN 108807308 A CN108807308 A CN 108807308A
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China
Prior art keywords
support construction
layer
metallic carrier
chip
encapsulating structure
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CN201710749776.7A
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CN108807308B (zh
Inventor
陈明志
许献文
蓝源富
徐宏欣
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Powertech Technology Inc
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Powertech Technology Inc
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Abstract

本发明提供一种封装结构及封装工艺方法。该封装结构包含金属载体、芯片、封模层及重配置线路层。金属载体包含底部及支撑结构，金属载体具有由底部及支撑结构共同形成凹陷部，且金属载体为一体成形。芯片设置于金属载体的凹陷部，且芯片具有多个导电凸块。封模层包覆芯片。封模层显露出每一导电凸块的一部分及支撑结构的一部分。重配置线路层设置于封模层上，且电连接于多个导电凸块。本发明能够通过刻蚀单一导电衬底使金属载体一体成形且具有凹陷部以作为容置芯片的散热槽，同时实作出能够提升抗电磁干扰、散热效果及结构强度的扇出结构。

Description

封装结构及封装工艺方法
技术领域
本发明有关于一种封装工艺方法，尤其是一种将芯片设置于一体成形的金属载体的凹陷部的封装工艺方法。
背景技术
在芯片的封装工艺中，常会利用到扇出结构。当芯片的输入/输出界面较多且输入/输出界面彼此间的间距较小时，扇出结构可通过将芯片的输入/输出界面经由扇出电路电连接至另一组具有较大间距的导电界面来扩张芯片的输入/输出界面之间的间距。利用扇出结构扩张输入/输出界面之间的间距能够提高良品率并简化封装工艺。前述的输入/输出界面可例如为球形栅格阵列(ball-grid-array，BGA)的焊接球。然而，前述的扇出结构虽然能够扩张输入/输出界面之间的间距，却在抗电磁干扰、散热效果及结构强度上不尽理想。
发明内容
本发明的一实施例提供一种封装结构，封装结构包含金属载体、芯片、封模层及重配置线路层。
金属载体包含底部及支撑结构，底部及支撑结构形成金属载体的凹陷部，且金属载体为一体成形。芯片设置于金属载体的凹陷部，芯片具有多个导电凸块。封模层包覆芯片，其中封模层显露出多个导电凸块的每一导电凸块的一部分及支撑结构的一部分。重配置线路层设置于封模层上，且电连接于多个导电凸块。
本发明的另一实施例提供一种封装工艺方法，方法包含形成金属载体，金属载体具有底部及支撑结构，底部及支撑结构形成金属载体的凹陷部，且金属载体为一体成形，将芯片设置于金属载体的凹陷部，形成封模层以包覆芯片，研磨封模层以显露出芯片的多个导电凸块的每一导电凸块的一部分及支撑结构的一部分，及于封模层上形成重配置线路层。重配置线路层电连接于多个导电凸块。
本发明能够通过刻蚀单一导电衬底使金属载体一体成形且具有凹陷部以作为容置芯片的散热槽，同时实作出能够提升抗电磁干扰、散热效果及结构强度的扇出结构。
附图说明
图1为本发明一实施例的封装结构的示意图。
图2为本发明另一实施例的封装结构的示意图。
图3为本发明一实施例的制造图1的封装结构的工艺方法的流程图。
图4至图10为对应于图3的各个步骤的封装结构示意图。
图11为本发明一实施例的制造图2的封装结构的工艺方法的流程图。
图12至图17为对应于图11的各个步骤的封装结构示意图。
图18为本发明一实施例的包含封装结构的层叠封装结构的示意图。
图19为本发明一实施例的一批次的封装结构的俯视图。
附图标号
100、200、1700 封装结构
110 金属载体
120 芯片
130 导电凸块
140、240 封模层
150、250 重配置线路层
160 第一焊接球
1101 底部
1102 第一支撑结构
1102e 外露表面
120c 功能界面
1501、2501 第一界面
1502、2502 第二界面
150c、250c 线路
170、2302 防焊层
f1 保护层
1101e 背侧表面
210 第二支撑结构
2101 第一附属界面
2102 第二附属界面
220 第二焊接球
2301、150p1、150p2、150pt、250p1、 介电层
250p2、250pt
300、1200 方法
310至360、1210至1288 步骤
110r 凹陷部
150m1、150m2、150mt、250m1、 导电层
250mt
1910 外接芯片
1915 界面
2011、2012 切割线
110i 间隙
210p 支柱
具体实施方式
图1为本发明一实施例的封装结构100的示意图。封装结构100可包含金属载体110、芯片120、多个导电凸块130、封模层140、重配置线路层150及多个第一焊接球160。金属载体110为一体成形，并可包含底部1101及第一支撑结构1102，且金属载体110的底部1101及第一支撑结构1102可形成金属载体110的凹陷部，其中第一支撑结构1102围绕着凹陷部。金属载体110同其底部1101及第一支撑结构1102可通过将单一导电衬底刻蚀来形成。通过以单一导电基体来成型，能够使金属载体110更强固而耐用。此外，底部1101可隔离电磁干扰以保护电路。金属载体110可具有低热容量。金属载体110的结构还可作为散热槽以助芯片120散热。因此封装结构100在抗电磁干扰、散热效果及结构强度方面都能够有所提升。
芯片120可具有多个功能界面120c。导电凸块130可对应地形成于功能界面120c。芯片120可设置在金属载体110的凹陷部以热耦合至底部1101。在芯片120及底部1101之间可设置保护层f1。保护层f1可为粘性层或薄膜，例如芯片粘结薄膜(die attach film，DAF)，以黏合芯片120及金属载体110。封模层140可通过在凹陷部中填入封模材料来形成，并可包覆芯片120。封模层140可被研磨至显露出导电凸块130及第一支撑结构1102的对应表面。如此一来，便能得到外露的导电凸块130及第一支撑结构1102的外露表面1102e。
在本发明的部分实施例中，第一支撑结构1102可电连接至接地端或电连接至电压源。重配置线路层150可形成于封模层140、外露的导电凸块130及第一支撑结构1102的外露表面1102e的上方，并可根据电路绕线的需求，包含一层或多层线路层。重配置线路层150可包含多个第一界面1501、线路150c及多个第二界面1502。第一界面1501可对应地耦接于外露的导电凸块130以及第一支撑结构1102的外露表面1102e。第二界面1502可经由线路150c电连接至重配置线路层150的第一界面1501。第一焊接球160可对应地设置于重配置线路层150的第二界面1502。
如图1所示，可通过形成防焊层170来覆盖重配置线路层150上除第二界面1502以外的部分。防焊层170可以在焊接过程中，保护重配置线路层150中除了第二界面1502以外的其他部分。
图2为本发明另一实施例的封装结构200的示意图。相较于图1中的封装结构100，封装结构200还可包含第二支撑结构210，第二支撑结构210可包含多个支柱210p，且支柱210p可如图19所示，环绕着第一支撑结构1102排列。在刻蚀金属载体110以形成底部1101及第一支撑结构1102时，也可同时一起形成第二支撑结构210。当凹陷部填入封模材料以形成封模层240之后，于刻蚀过程中所产生的空间，例如第一支撑结构1102与第二支撑结构210之间的空隙，以及多个支柱210p之间的空隙，都将由封模层240填充。封模层240固化后可被研磨至显露出第一外露面(外露于封模层240)，以形成多个第一附属界面2101。
部分在第一支撑结构1102与第二支撑结构210之间以及在多个支柱210p之间的底部1101可通过刻蚀封装结构200的背面(亦即封装结构200中相对于芯片120较靠近底部1101的这一面)来移除，以形成第二外露面(同样外露于封模层240)并藉此形成多个第二附属界面2102，同时也使多个支柱210p彼此之间及多个支柱210p与第一支撑结构1102保持电性隔离。封装结构200的整个背面，包含外露的封模层240及多个第二附属界面2102，可由介电层2301覆盖。防焊层2302可形成于介电层2301上方，并可覆盖以保护除了在第二附属界面2102上方以外的介电层2301。在第二附属界面2102上方的介电层2301可接着被移除，以使在第二附属界面2102上的第二焊接球220能够电连接至下一个接续的半导体封装，如图18所示。
在图2中，重配置线路层250与图1的重配置线路层150相似，并可形成于封模层240上方。重配置线路层250的第一界面2501可设置于导电凸块130、第一支撑结构1102的外露表面1102e及第一附属界面2101的上方。如图2所述，部分的介电层2301及部分的防焊层2302可被移除或不设置，藉以显露出金属载体110的底部1101，达到较好的散热效果。由于底部1101可作为电磁干扰的屏蔽以及散热槽，因此将底部1101外露即可进一步提升散热效果。在部分其他的实施例中，底部1101也可由介电层2301及/或防焊层2302所覆盖。
在部分实施例中，图1的重配置线路层150及图2的重配置线路层250可包含多个介电层及多个导电层。重配置线路层150及250的介电层与导电层可根据需求形成客制化的线路。重配置线路层150及250可包含根据需求所设计的线路，并可用来将芯片120上具有较小间距的功能界面120c重新配置连接。重配置线路层150及250可提供扇出线路以将功能界面120c之间的狭小间距扩张至焊接球之间的较大间距。在部分实施例中，重配置线路层150及250的介电层可包含可与对应波长光显影成型的至少一感光层。在部分实施例中，重配置线路层150及250还可包含至少一金种溅射层。
如图1及图2所示，第一支撑结构1102及第二支撑结构210可作为加强结构的支撑柱。第一支撑结构1102可被刻蚀至所需的大小，以提升散热能力。第二支撑结构210可被形成为一组电性隔离的支柱。
图3为本发明一实施例的制造图1的封装结构100的工艺方法300的流程图。图4至图10为封装结构100对应于图3的各个步骤的示意图。封装工艺方法300可包含步骤310至360。
步骤310：将单一导电衬底刻蚀以形成一体成型且具有凹陷部110r的金属载体110；
步骤320：将芯片120设置于金属载体110的凹陷部110r；
步骤330：利用封模材料填充凹陷部110r以形成包覆芯片120的封模层140；
步骤340：研磨封模层140以显露出导电凸块130的对应表面；
步骤350：于封模层140上形成重配置线路层150，使得重配置线路层150的第一界面1501能够对应地耦接至外露的导电凸块130；
步骤360：将第一焊接球160设置于重配置线路层150的第二界面1502，且第一焊接球160可经由重配置线路层150的线路150c电连接至功能界面120c。
图4可对应于步骤310。图5可对应于步骤320。图6可对应于步骤330至340。图7至图9可对应于步骤350。图10可对应于步骤360。
在步骤310中，凹陷部110r的底部1101可实质上与第一支撑结构1102形成直角。由于刻蚀的过程，底部1101可能并非完全平整。然而，底部1101的不平整通常可以忽略，而芯片120的大小可小到足以让芯片120能够稳定地设置于凹陷部110r中。如图5所示，保护层f1可形成于芯片120及凹陷部110r之间，以在步骤320中将芯片120黏合至底部1101。
导电凸块130可为通过柱状凸块工艺(pillar bump process)所形成或设置的铜柱，并可对应地电连接至芯片120的功能界面120c。在部分实施例中，导电凸块130可能在芯片120设置于金属载体110之前就已经先行形成。除了铜以外，其他适合的导电材料也可用来形成导电凸块130。
在步骤360中，防焊层170可在焊接过程中，保护重配置线路层150中除了界面1502以外的部分。如图7至图9所示，介电层150p1、150p2及150pt和导电层150m1、150m2及150mt可通过光罩显影图案的方式一层一层制作来形成重配置线路层150。
导电层150m1、150m2及150mt可通过移除不需要的部分来形成所需的图案。第一光刻胶层、第二光刻胶层及第三光刻胶层可分别用来形成导电层150m1、150m2及150mt的图案。线路150c可利用至少导电层150m1、150m2及150mt来形成。在图7至图10中，重配置线路层150可包含三层介电层及三层导电层。然而，图7至图10是为方便说明所提供的实施例。在本发明的其他实施例中，重配置线路层150也可能根据需求而包含其他数量的介电层及导电层。举例来说，根据本发明的一实施例，重配置线路层150也可仅包含一层介电层及一层导电层即可形成重配置线路层150的第一界面1501及第二界面1502。在其他实施例中，重配置线路层150可包含至少一介电层及至少一导电层。另可将适合的材料设置于界面1502以作为与第一焊接球160相接的球下冶金层(under bump metallurgy，UBM)。
由于上述的工艺能够制作多个彼此相连、形成阵列的封装结构100，因此在封装结构100制作完毕后，还可通过切割程序(亦即分离程序)来将多个封装结构100彼此分离。切割程序可包含机械锯切、激光切割或其他切割方法。
图11为本发明一实施例的制造图2的封装结构200的工艺方法1200的流程图。图12至图17为封装结构200对应于图11的各个步骤的示意图。封装工艺方法1200可包含步骤1210至1288。
步骤1210：将单一导电衬底刻蚀以形成具有底部1101、第一支撑结构1102及第二支撑结构210的金属载体110，底部1101及第一支撑结构1102可共同形成凹陷部110r，而第一支撑结构1102及第二支撑结构210之间可形成间隙110i；
步骤1220：将芯片120设置于金属载体110的凹陷部110r；
步骤1230：利用封模材料填充凹陷部110r及间隙110i以形成包覆芯片120的封模层240；
步骤1240：研磨封模层240以显露出导电凸块130，并显露出第一支撑结构1102及第二支撑结构210以取得第一支撑结构1102的外露表面1102e及第二支撑结构210的第一附属界面2101；
步骤1250：于封模层240、第一支撑结构1102的外露表面1102e及第二支撑结构210的第一附属界面2101上形成重配置线路层250，使得重配置线路层250能够对应地将其第一界面2501耦接至外露的导电凸块130、第一支撑结构1102的外露表面1102e及第一附属界面2101；
步骤1260：将第一焊接球160设置于重配置线路层250的第二界面2502，使得第一焊接球160能够经由重配置线路层250的线路250c与芯片120的功能界面120c有电连接；
步骤1270：刻蚀金属载体110的底部1101以使第一支撑结构1102及第二支撑结构210分离；
步骤1280：形成介电层2301以使第一支撑结构1102与第二支撑结构210在显露出第二附属界面2102的情况下保持隔离；
步骤1285：形成防焊层2302以覆盖介电层2301，且防焊层2301具有图案以显露出第二附属界面2102；
步骤1288：于第二附属界面2102上设置第二焊接球220。
图12可对应于步骤1210。图13可对应于步骤1220。图14可对应于步骤1230至1240。图15至图17可对应于步骤1250至1288。在步骤1240中，研磨程序可以移除封模层240中不需要的部分。
在步骤1210中，根据本发明的其他实施例，除了第一支撑结构1102及第二支撑结构210外，还可形成更多数量的支撑结构。多个支撑结构可用以形成支柱阵列以利层叠封装时提供所需的电连接。支柱间的间隔可以根据半导体封装的需求增大或缩小。在步骤1220至1240中，会形成可容置芯片120并形成封模层240的凹陷部110r。在步骤1250至1260中，可形成重配置线路层250(如图2所示)。此外，第一焊接球160可设置于重配置线路层250上方。在步骤1270中，通过刻蚀金属载体110的底部1102即可使第一支撑结构1102及第二支撑结构210相分离。再者，第二支撑结构210可通过刻蚀来形成多个支柱。第二支撑结构210所形成的支柱可例如以下所述及图19的俯视图所示的支柱210p。
重配置线路层250与前述的重配置线路层150相似，重配置线路层250可包含介电层250p1、250p2及250pt，以及导电层250m1及250mt，亦即如图2、图15及图16所示。重配置线路层250的介电层可利用钻孔方式形成通路。重配置线路层250的导电层可形成具有特定图案并能够通过介电层的通路连接至其他的导电层以形成线路250c。图2、图15及图16中，重配置线路层250中的介电层的数量及导电层的数量仅为方便说明的实施例。重配置线路层250可根据需求形成任意数量的介电层及导电层。第一导电层250m1及/或顶部导电层250mt可与溅射的传导性接种层(conductive seed)一起电镀以提升焊接球的焊接准确度。通过执行表面抛光程序还可清洁界面2502及第二附属界面2102并使其平整，以便固定焊接球160及220。如图2所示，底部1101的至少一部分可外露，以达到较佳的散热效果。如同先前所述，在多个共同形成且彼此具有物理连接的封装结构200制作完成后，还可执行切割程序以将这些封装结构200彼此分离。
图17为本发明一实施例的封装结构1700的示意图。封装结构1700与图2的封装结构200相似。然而，如图17所示，此实施例的散热槽(亦即金属载体110)的背侧还覆盖了介电层及防焊层。在图17中，底部1101可被介电层2301及防焊层2302覆盖，并仅显露出第二附属界面2102。在本发明的部分实施例中，图2的封装结构200可通过对图17的封装结构1700执行其他程序来制作。在图17中，若移除部分的介电层2301及对应部分的防焊层2302即可显露出散热槽的背侧表面1101e，提升散热效果。根据本发明的实施例所提供的封装结构100(图1)、200(图2)及1700(图17)，(具导电性的)支撑结构1102及210能够提升散热槽(亦即金属载体110)的支撑强度，并可作为导电通路以提升设计的弹性，还可提供良好的散热及抗电磁干扰(electromagnetic interference，EMI)效果。使用者可以根据产品的规格选择适当类型的封装结构。
图18为本发明一实施例的包含封装结构200的层叠封装(package-on-package，PoP)结构的示意图。外部芯片1910可设置于第二焊接球220以使外接芯片1910的多个界面1915与第二焊接球220相耦接。外接芯片1910可通过第二焊接球220、第二支撑结构210所形成的一组支柱、线路250c及导电凸块130与芯片120电性通联。
图19为本发明一实施例的一批次的封装结构的俯视图。如同先前所述，在图19中，第二支撑结构210可具有一组排列成方形的支柱210p。第一支撑结构1102可围绕芯片120以提供电磁屏蔽。在图19中，多个封装结构可形成如阵列。例如在图19所示的四个封装结构。在封装结构制作完成后，可沿着切割线2011至2012执行切割程序来将各个封装结构分离。
综上所述，通过本发明的实施例所提供的封装工艺方法及封装结构，就能够通过刻蚀单一导电衬底使金属载体一体成形且具有凹陷部以作为容置芯片的散热槽，同时实作出能够提升抗电磁干扰、散热效果及结构强度的扇出结构。且在此架构下，还可允许层叠封装结构。
以上所述仅为本发明的较佳实施例，凡依本发明申请专利范围所做的均等变化与修饰，皆应属本发明的涵盖范围。

Claims (10)

1.一种封装结构，其特征在于，包含：
一金属载体，包含一底部及一第一支撑结构，该底部及该第一支撑结构形成该金属载体的一凹陷部，该金属载体为一体成形，且该金属载体的该底部暴露于该封装结构外；
一芯片，设置于该金属载体的该凹陷部，该芯片具有多个导电凸块；
一封模层，包覆该芯片，其中该封模层显露出该多个导电凸块的每一导电凸块的一部分及该第一支撑结构的一部分；及
一重配置线路层，设置于该封模层上，且电连接于该多个导电凸块。
2.如权利要求1所述的封装结构，其特征在于，该金属载体另包含一第二支撑结构，设置于该第一支撑结构周围，该第二支撑结构电连接至该重配置线路层，并由该封模层包覆，及该第二支撑结构包含多个支柱。
3.如权利要求2所述的封装结构，其特征在于，该底部的至少一部分及该第二支撑结构的至少一部分被一介电层覆盖。
4.如权利要求1所述的封装结构，其特征在于，该第一支撑结构电连接于该重配置线路层。
5.如权利要求1所述的封装结构，其特征在于，另包含：
一保护层，设置于该芯片及该金属载体之间。
6.一种封装工艺方法，其特征在于，包含：
形成一金属载体，该金属载体具有一底部及多个支撑结构，该底部及该多个支撑结构中的一第一支撑结构形成该金属载体的一凹陷部，且该金属载体为一体成形；
将一芯片设置于该金属载体的该凹陷部；
形成一封模层以包覆该芯片；
研磨该封模层以显露出该芯片的多个导电凸块的每一导电凸块的一部分及该多个支撑结构的一部分；及
于该封模层上形成一重配置线路层，其中该重配置线路层电连接于该多个导电凸块。
7.如权利要求6所述的方法，其特征在于，另包含：
在该芯片及该金属载体的该底部之间设置一保护层。
8.如权利要求6所述的方法，其特征在于，形成该金属载体是将一单一导电衬底刻蚀以形成该底部及该多个支撑结构。
9.如权利要求8所述的方法，其特征在于，另包含：
在形成该封模层后，刻蚀该金属载体以使该多个支撑结构中的一第二支撑结构区隔于该底部及该第一支撑结构；
其中该第二支撑结构包含多个支柱。
10.如权利要求9所述的方法，其特征在于，另包含：
形成一介电层以覆盖该底部的至少一部分及该第二支撑结构的至少一部分。
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