CN108028243B - 使用空腔结构的晶片级封装(wlp)球型支撑 - Google Patents

使用空腔结构的晶片级封装(wlp)球型支撑 Download PDF

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Publication number
CN108028243B
CN108028243B CN201680053950.8A CN201680053950A CN108028243B CN 108028243 B CN108028243 B CN 108028243B CN 201680053950 A CN201680053950 A CN 201680053950A CN 108028243 B CN108028243 B CN 108028243B
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China
Prior art keywords
dielectric layer
conductive pads
cavities
adhesive
conductors
Prior art date
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CN201680053950.8A
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English (en)
Chinese (zh)
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CN108028243A (zh
Inventor
M·F·维纶茨
D·F·伯蒂
C·H·尹
J·金
C·左
D·D·金
J-H·J·兰
N·S·慕达卡特
R·P·米库尔卡
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Qualcomm Inc
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Qualcomm Inc
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Publication of CN108028243A publication Critical patent/CN108028243A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/936—Multiple bond pads having different shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W80/00—Direct bonding of chips, wafers or substrates
    • H10W80/701—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding
    • H10W80/732—Direct bonding of chips, wafers or substrates characterised by the pads after the direct bonding having shape changed during the connecting

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
CN201680053950.8A 2015-09-20 2016-09-20 使用空腔结构的晶片级封装(wlp)球型支撑 Active CN108028243B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/859,323 US10074625B2 (en) 2015-09-20 2015-09-20 Wafer level package (WLP) ball support using cavity structure
US14/859,323 2015-09-20
PCT/US2016/052631 WO2017049324A1 (en) 2015-09-20 2016-09-20 Wafer level package (wlp) ball support using cavity structure

Publications (2)

Publication Number Publication Date
CN108028243A CN108028243A (zh) 2018-05-11
CN108028243B true CN108028243B (zh) 2021-05-14

Family

ID=57018210

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201680053950.8A Active CN108028243B (zh) 2015-09-20 2016-09-20 使用空腔结构的晶片级封装(wlp)球型支撑

Country Status (8)

Country Link
US (1) US10074625B2 (https=)
EP (1) EP3350831A1 (https=)
JP (1) JP6549790B2 (https=)
KR (1) KR102006115B1 (https=)
CN (1) CN108028243B (https=)
BR (1) BR112018005532B1 (https=)
CA (1) CA2995621A1 (https=)
WO (1) WO2017049324A1 (https=)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20240057513A (ko) 2022-10-24 2024-05-03 삼성전자주식회사 반도체 패키지

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100319974A1 (en) * 2008-02-19 2010-12-23 Naomi Ishizuka Printed wiring board, electronic device, and method for manufacturing electronic device

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JP3019851B1 (ja) * 1998-12-22 2000-03-13 日本電気株式会社 半導体装置実装構造
GB2389460A (en) 1998-12-22 2003-12-10 Nec Corp Mounting semiconductor packages on substrates
JP3446825B2 (ja) * 1999-04-06 2003-09-16 沖電気工業株式会社 半導体装置およびその製造方法
JP2002050716A (ja) * 2000-08-02 2002-02-15 Dainippon Printing Co Ltd 半導体装置及びその作製方法
JP3842548B2 (ja) * 2000-12-12 2006-11-08 富士通株式会社 半導体装置の製造方法及び半導体装置
US6818545B2 (en) * 2001-03-05 2004-11-16 Megic Corporation Low fabrication cost, fine pitch and high reliability solder bump
JP2003198068A (ja) 2001-12-27 2003-07-11 Nec Corp プリント基板、半導体装置、およびプリント基板と部品との電気的接続構造
US6854633B1 (en) * 2002-02-05 2005-02-15 Micron Technology, Inc. System with polymer masking flux for fabricating external contacts on semiconductor components
JP2004103928A (ja) * 2002-09-11 2004-04-02 Fujitsu Ltd 基板及びハンダボールの形成方法及びその実装構造
US7043830B2 (en) 2003-02-20 2006-05-16 Micron Technology, Inc. Method of forming conductive bumps
US8193092B2 (en) * 2007-07-31 2012-06-05 Micron Technology, Inc. Semiconductor devices including a through-substrate conductive member with an exposed end and methods of manufacturing such semiconductor devices
JP2012221998A (ja) * 2011-04-04 2012-11-12 Toshiba Corp 半導体装置ならびにその製造方法
JP5682496B2 (ja) * 2011-07-28 2015-03-11 富士通セミコンダクター株式会社 半導体装置、マルチチップ半導体装置、デバイス、及び半導体装置の製造方法
KR101840447B1 (ko) * 2011-08-09 2018-03-20 에스케이하이닉스 주식회사 반도체 패키지 및 이를 갖는 적층 반도체 패키지
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Also Published As

Publication number Publication date
EP3350831A1 (en) 2018-07-25
JP6549790B2 (ja) 2019-07-24
JP2018527754A (ja) 2018-09-20
WO2017049324A1 (en) 2017-03-23
CN108028243A (zh) 2018-05-11
CA2995621A1 (en) 2017-03-23
US20170084565A1 (en) 2017-03-23
US10074625B2 (en) 2018-09-11
KR102006115B1 (ko) 2019-07-31
BR112018005532B1 (pt) 2023-03-07
BR112018005532A2 (https=) 2018-10-02
KR20180056686A (ko) 2018-05-29

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