JP2018514891A5 - - Google Patents

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JP2018514891A5
JP2018514891A5 JP2017543727A JP2017543727A JP2018514891A5 JP 2018514891 A5 JP2018514891 A5 JP 2018514891A5 JP 2017543727 A JP2017543727 A JP 2017543727A JP 2017543727 A JP2017543727 A JP 2017543727A JP 2018514891 A5 JP2018514891 A5 JP 2018514891A5
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JP
Japan
Prior art keywords
reference voltage
ferroelectric memory
memory cell
integrated circuit
data state
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JP2017543727A
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Japanese (ja)
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JP2018514891A (ja
JP6769975B2 (ja
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Priority claimed from US15/019,026 external-priority patent/US9767879B2/en
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JP2017543727A 2015-02-17 2016-02-16 強誘電体メモリにおけるデータ感知のための基準電圧の設定 Active JP6769975B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562116977P 2015-02-17 2015-02-17
US62/116,977 2015-02-17
US15/019,026 2016-02-09
US15/019,026 US9767879B2 (en) 2015-02-17 2016-02-09 Setting of reference voltage for data sensing in ferroelectric memories
PCT/US2016/018011 WO2016133869A1 (en) 2015-02-17 2016-02-16 Setting of reference voltage for data sensing in ferroelectric memories

Publications (3)

Publication Number Publication Date
JP2018514891A JP2018514891A (ja) 2018-06-07
JP2018514891A5 true JP2018514891A5 (enExample) 2019-03-28
JP6769975B2 JP6769975B2 (ja) 2020-10-14

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JP2017543727A Active JP6769975B2 (ja) 2015-02-17 2016-02-16 強誘電体メモリにおけるデータ感知のための基準電圧の設定

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US (2) US9767879B2 (enExample)
JP (1) JP6769975B2 (enExample)
CN (1) CN107210062B (enExample)
WO (1) WO2016133869A1 (enExample)

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* Cited by examiner, † Cited by third party
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US10847201B2 (en) * 2019-02-27 2020-11-24 Kepler Computing Inc. High-density low voltage non-volatile differential memory bit-cell with shared plate line
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US9767879B2 (en) * 2015-02-17 2017-09-19 Texas Instruments Incorporated Setting of reference voltage for data sensing in ferroelectric memories
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