JP2018513520A5 - - Google Patents

Download PDF

Info

Publication number
JP2018513520A5
JP2018513520A5 JP2017548466A JP2017548466A JP2018513520A5 JP 2018513520 A5 JP2018513520 A5 JP 2018513520A5 JP 2017548466 A JP2017548466 A JP 2017548466A JP 2017548466 A JP2017548466 A JP 2017548466A JP 2018513520 A5 JP2018513520 A5 JP 2018513520A5
Authority
JP
Japan
Prior art keywords
power supply
gate
supply voltage
word line
line driver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2017548466A
Other languages
English (en)
Japanese (ja)
Other versions
JP6352552B2 (ja
JP2018513520A (ja
Filing date
Publication date
Priority claimed from US15/070,963 external-priority patent/US9940987B2/en
Application filed filed Critical
Publication of JP2018513520A publication Critical patent/JP2018513520A/ja
Application granted granted Critical
Publication of JP6352552B2 publication Critical patent/JP6352552B2/ja
Publication of JP2018513520A5 publication Critical patent/JP2018513520A5/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2017548466A 2015-03-16 2016-03-16 高速ワードラインデコーダおよびレベルシフタ Expired - Fee Related JP6352552B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201562133840P 2015-03-16 2015-03-16
US62/133,840 2015-03-16
US15/070,963 US9940987B2 (en) 2015-03-16 2016-03-15 High-speed word line decoder and level-shifter
US15/070,963 2016-03-15
PCT/US2016/022593 WO2016149333A1 (en) 2015-03-16 2016-03-16 High-speed word line decoder and level-shifter

Publications (3)

Publication Number Publication Date
JP2018513520A JP2018513520A (ja) 2018-05-24
JP6352552B2 JP6352552B2 (ja) 2018-07-04
JP2018513520A5 true JP2018513520A5 (enExample) 2018-07-05

Family

ID=55661580

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017548466A Expired - Fee Related JP6352552B2 (ja) 2015-03-16 2016-03-16 高速ワードラインデコーダおよびレベルシフタ

Country Status (6)

Country Link
US (1) US9940987B2 (enExample)
EP (1) EP3271919B1 (enExample)
JP (1) JP6352552B2 (enExample)
KR (1) KR101956615B1 (enExample)
CN (1) CN107430876B (enExample)
WO (1) WO2016149333A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104811634B (zh) * 2013-12-29 2018-07-31 芯视达系统公司 支持多种电压的紧凑型行解码器
US10037290B1 (en) * 2016-06-02 2018-07-31 Marvell International Ltd. Dual-port memories and input/output circuits for preventing failures corresponding to concurrent accesses of dual-port memory cells
US10109365B2 (en) * 2016-11-28 2018-10-23 Taiwan Semiconductor Manufacturing Company Limited Word line driver
US11114148B1 (en) * 2020-04-16 2021-09-07 Wuxi Petabyte Technologies Co., Ltd. Efficient ferroelectric random-access memory wordline driver, decoder, and related circuits
US11264093B1 (en) * 2020-08-25 2022-03-01 Taiwan Semiconductor Manufacturing Company Limited Duo-level word line driver

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000187977A (ja) 1998-12-21 2000-07-04 Mitsubishi Electric Corp 半導体記憶装置
JP2004334982A (ja) * 2003-05-08 2004-11-25 Nec Electronics Corp 行デコーダ、半導体回路装置
JP4496069B2 (ja) * 2004-12-20 2010-07-07 株式会社東芝 Ｍｏｓ型半導体集積回路装置
US7176725B2 (en) * 2005-02-04 2007-02-13 International Business Machines Corporation Fast pulse powered NOR decode apparatus for semiconductor devices
US7463545B2 (en) 2006-03-17 2008-12-09 Texas Instruments Incorporated System and method for reducing latency in a memory array decoder circuit
JP2008084457A (ja) 2006-09-28 2008-04-10 Toshiba Corp 不揮発性半導体記憶装置
JP2008152845A (ja) * 2006-12-15 2008-07-03 Toshiba Corp 半導体記憶装置
JP4913878B2 (ja) * 2009-05-27 2012-04-11 ルネサスエレクトロニクス株式会社 ワード線選択回路、ロウデコーダ
US8391097B2 (en) 2010-05-25 2013-03-05 Taiwan Semiconductor Manufacturing Co. Ltd. Memory word-line driver having reduced power consumption
KR101753251B1 (ko) 2010-07-23 2017-07-05 삼성전자주식회사 음전압 레벨 쉬프터를 포함하는 스태틱 랜덤 액세스 메모리 장치
US8456946B2 (en) 2010-12-22 2013-06-04 Intel Corporation NAND logic word line selection
US9299395B2 (en) 2012-03-26 2016-03-29 Intel Corporation Methods and systems to selectively boost an operating voltage of, and controls to an 8T bit-cell array and/or other logic blocks
US9325314B2 (en) 2012-12-07 2016-04-26 Samsung Electronics Co., Ltd. Integrated circuit including circuits driven in different voltage domains
US8971133B1 (en) 2013-09-26 2015-03-03 Arm Limited Memory device and method of operation of such a memory device

Similar Documents

Publication Publication Date Title
JP2018513520A5 (enExample)
JP2019169233A5 (enExample)
JP2014180213A5 (enExample)
JP2016518785A5 (enExample)
TW201714409A (zh) 積體時脈閘控單元
TW201514991A (zh) 記憶體及其操作電壓開關電路的方法
US8432189B1 (en) Digital voltage level shifter
JP6352552B2 (ja) 高速ワードラインデコーダおよびレベルシフタ
US7982505B2 (en) Logic circuit, address decoder circuit and semiconductor memory
US9432002B2 (en) High-speed voltage level shifter circuit
CN202549251U (zh) 一种led显示屏消隐控制电路及led驱动芯片
US9293181B2 (en) Block selection circuit and semiconductor device having the same
KR100951666B1 (ko) 테스트 모드를 제어하는 반도체 집적 회로
TW200537498A (en) Redundancy circuit for NAND flash memory device
RU2014103732A (ru) Радиационно стойкая энергонезависимая программируемая логическая интегральная схема
US20150288350A1 (en) Signal transfer circuit and operating method thereof
CN104835529B (zh) 用于半导体装置的冗余评估电路
US20130163358A1 (en) Systems, circuits, and methods for charge sharing
US20150279451A1 (en) Edge-triggered pulse latch
TWI559302B (zh) 驅動次字元線之半導體記憶體元件
US20120163115A1 (en) Nor logic word line selection
CN106297868B (zh) 驱动子字线的半导体存储器元件
US20090085637A1 (en) Apparatus effecting interface between differing signal levels
TWI523020B (zh) 用於半導體裝置的冗餘評估電路
KR20130095804A (ko) Ｎａｎｄ 논리 워드 라인 선택