JP2018502406A - マルチチャネルｉ２ｓ伝送制御システムおよび方法 - Google Patents

マルチチャネルｉ２ｓ伝送制御システムおよび方法 Download PDF

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Publication number
JP2018502406A
JP2018502406A JP2017544557A JP2017544557A JP2018502406A JP 2018502406 A JP2018502406 A JP 2018502406A JP 2017544557 A JP2017544557 A JP 2017544557A JP 2017544557 A JP2017544557 A JP 2017544557A JP 2018502406 A JP2018502406 A JP 2018502406A
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Japan
Prior art keywords
bits
memory line
transmission unit
bit
transmission
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JP2017544557A
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Japanese (ja)
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JP2018502406A5 (https=
Inventor
ジェイムズ カサディー，
ジェイムズ カサディー，
ロドニー ペサベント，
ロドニー ペサベント，
セルゲイ パブロフ，
セルゲイ パブロフ，
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Microchip Technology Inc
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Microchip Technology Inc
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Application filed by Microchip Technology Inc filed Critical Microchip Technology Inc
Publication of JP2018502406A publication Critical patent/JP2018502406A/ja
Publication of JP2018502406A5 publication Critical patent/JP2018502406A5/ja
Pending legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
JP2017544557A 2014-11-11 2015-11-09 マルチチャネルｉ２ｓ伝送制御システムおよび方法 Pending JP2018502406A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/538,133 US9842071B2 (en) 2014-11-11 2014-11-11 Multi-channel I2S transmit control system and method
US14/538,133 2014-11-11
PCT/US2015/059661 WO2016077189A1 (en) 2014-11-11 2015-11-09 Multi-channel i2s transmit control system and method

Publications (2)

Publication Number Publication Date
JP2018502406A true JP2018502406A (ja) 2018-01-25
JP2018502406A5 JP2018502406A5 (https=) 2018-11-29

Family

ID=54705814

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017544557A Pending JP2018502406A (ja) 2014-11-11 2015-11-09 マルチチャネルｉ２ｓ伝送制御システムおよび方法

Country Status (7)

Country Link
US (1) US9842071B2 (https=)
EP (1) EP3218813B1 (https=)
JP (1) JP2018502406A (https=)
KR (1) KR20170084043A (https=)
CN (1) CN107111587A (https=)
TW (1) TW201633164A (https=)
WO (1) WO2016077189A1 (https=)

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GB2539445A (en) * 2015-06-16 2016-12-21 Nordic Semiconductor Asa Data processing
US10007485B2 (en) * 2016-01-12 2018-06-26 Oracle International Corporation Zero-delay compression FIFO buffer
CN106911987B (zh) * 2017-02-21 2019-11-05 珠海全志科技股份有限公司 主控端、设备端、传输多声道音频数据的方法和系统
CN108628793B (zh) * 2017-03-20 2021-04-02 华大半导体有限公司 Spi通信电路及方法
FR3066033B1 (fr) * 2017-05-05 2019-06-21 Stmicroelectronics (Rousset) Sas Dispositif d'etage tampon, en particulier apte a etre connecte sur un bus du type interface de peripherique serie
CN108304282B (zh) * 2018-03-07 2021-04-20 郑州云海信息技术有限公司 一种双bios的控制方法及相关装置
TWI699656B (zh) * 2018-12-27 2020-07-21 新唐科技股份有限公司 可切換的i2s介面
DE102019112447A1 (de) * 2019-05-13 2020-11-19 Jenoptik Optical Systems Gmbh Verfahren und Auswerteeinheit zur Ermittlung eines Zeitpunkts einer Flanke in einem Signal
DE112020004915T5 (de) * 2019-10-10 2022-06-30 Microchip Technology Incorporated Serielle n-kanal-peripheriekommunikation und darauf bezogene systeme, verfahren und vorrichtungen
IT202000006322A1 (it) 2020-03-25 2021-09-25 Stmicroelectronics Application Gmbh Sistema di elaborazione comprendente un’interfaccia periferica seriale con code, relativo circuito integrato, dispositivo e procedimento
RU2762040C1 (ru) * 2020-11-06 2021-12-15 СВИ Коммуникатионс-унд Компутер ГмбХ Система объединения цифровых потоков и способ объединения цифровых потоков (варианты)

Citations (3)

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JP2004240713A (ja) * 2003-02-06 2004-08-26 Matsushita Electric Ind Co Ltd データ転送方法及びデータ転送装置
JP2004248279A (ja) * 2003-02-12 2004-09-02 Thomson Licensing Sa 異なるタイプのインタフェースからの入力信号、又は異なるタイプのインタフェースへの出力信号を共通フォーマットの中央演算処理でプリプロセスするための方法及び装置
US20080244120A1 (en) * 2007-03-27 2008-10-02 Samsung Electronics Co., Ltd. Multi-protocol serial interface apparatus and system-on-chip apparatus including the same

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US5517627A (en) * 1992-09-18 1996-05-14 3Com Corporation Read and write data aligner and method
JP4354268B2 (ja) * 2003-12-22 2009-10-28 株式会社河合楽器製作所 信号処理装置
EP2294858A4 (en) * 2008-06-23 2014-07-02 Hart Comm Foundation ANALYZER FOR A WIRELESS COMMUNICATION NETWORK
US8255593B2 (en) * 2009-09-29 2012-08-28 Oracle America, Inc. Direct memory access with striding across memory
US20110242355A1 (en) * 2010-04-05 2011-10-06 Qualcomm Incorporated Combining data from multiple image sensors
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Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004240713A (ja) * 2003-02-06 2004-08-26 Matsushita Electric Ind Co Ltd データ転送方法及びデータ転送装置
JP2004248279A (ja) * 2003-02-12 2004-09-02 Thomson Licensing Sa 異なるタイプのインタフェースからの入力信号、又は異なるタイプのインタフェースへの出力信号を共通フォーマットの中央演算処理でプリプロセスするための方法及び装置
US20080244120A1 (en) * 2007-03-27 2008-10-02 Samsung Electronics Co., Ltd. Multi-protocol serial interface apparatus and system-on-chip apparatus including the same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
BURNS, MICHAEL: "INTERFACING AN I2S DEVICE TO AN MSP430 DEVICE", [ONLINE], JPN5017009403, 31 March 2010 (2010-03-31), US, pages 1 - 7, ISSN: 0004068999 *

Also Published As

Publication number Publication date
EP3218813A1 (en) 2017-09-20
EP3218813B1 (en) 2022-05-04
US9842071B2 (en) 2017-12-12
KR20170084043A (ko) 2017-07-19
CN107111587A (zh) 2017-08-29
WO2016077189A1 (en) 2016-05-19
TW201633164A (zh) 2016-09-16
US20160132440A1 (en) 2016-05-12

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