WO2016188344A1 - 一种基于软处理器的图像信号源及其处理图像信号的方法 - Google Patents

一种基于软处理器的图像信号源及其处理图像信号的方法 Download PDF

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Publication number
WO2016188344A1
WO2016188344A1 PCT/CN2016/082324 CN2016082324W WO2016188344A1 WO 2016188344 A1 WO2016188344 A1 WO 2016188344A1 CN 2016082324 W CN2016082324 W CN 2016082324W WO 2016188344 A1 WO2016188344 A1 WO 2016188344A1
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module
control block
programmable logic
image signal
program
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PCT/CN2016/082324
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English (en)
French (fr)
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彭骞
付文明
叶金平
沈亚非
陈凯
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武汉精测电子技术股份有限公司
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Priority to JP2017561953A priority Critical patent/JP6554184B2/ja
Priority to KR1020177037480A priority patent/KR102012120B1/ko
Publication of WO2016188344A1 publication Critical patent/WO2016188344A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/25—Management operations performed by the server for facilitating the content distribution or administrating data related to end-users or client devices, e.g. end-user or client device authentication, learning user preferences for recommending movies
    • H04N21/262—Content or additional data distribution scheduling, e.g. sending additional data at off-peak times, updating software modules, calculating the carousel transmission frequency, delaying a video stream transmission, generating play-lists
    • H04N21/26291—Content or additional data distribution scheduling, e.g. sending additional data at off-peak times, updating software modules, calculating the carousel transmission frequency, delaying a video stream transmission, generating play-lists for providing content or additional data updates, e.g. updating software modules, stored at the client
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/14—Picture signal circuitry for video frequency region
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/433—Content storage operation, e.g. storage operation in response to a pause request, caching operations
    • H04N21/4331—Caching operations, e.g. of an advertisement for later insertion during playback
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/60—Network structure or processes for video distribution between server and client or between remote clients; Control signalling between clients, server and network components; Transmission of management data between server and client, e.g. sending from server to client commands for recording incoming content stream; Communication details between server and client 
    • H04N21/63—Control signaling related to video distribution between client, server and network components; Network processes for video distribution between server and clients or between remote clients, e.g. transmitting basic layer and enhancement layers over different transmission paths, setting up a peer-to-peer communication via Internet between remote STB's; Communication protocols; Addressing
    • H04N21/643—Communication protocols

Definitions

  • the invention belongs to the technical field of image signal sources, and in particular relates to an image signal source based on a soft processor and a method for processing the same.
  • the current image signal source is based on a hard processor (ARM) cooperative programmable logic device (FPGA).
  • ARM hard processor
  • FPGA programmable logic device
  • the first image is output for a long time. Since the image data of the ARM architecture is stored in the flash of the ARM peripheral, after power-on, the ARM must be started first. After the startup is completed, the image data is read from the flash. In ARM's DDR, the data is read from the ARM DDR and transmitted to the DDR of the FPGA through the interconnect bus. The FPGA internal control logic block reads the image data from the DDR of the FPGA and outputs it to the image output interface. The whole process is complicated. It caused the first time to power up the first picture for too long.
  • image data transmission efficiency is low, whether it is online output image signal or offline output image signal
  • the image signal is first processed by ARM, after the ARM processing is completed, it is transmitted to the FPGA through the interconnect bus, and then the FPGA outputs the type according to the image signal. After processing, output through different interfaces, the whole process is cumbersome, resulting in low image signal output efficiency.
  • the architecture is complex and costly, the image signal source of ARM architecture needs to be completed by ARM plus FPGA, which makes the hardware architecture and software architecture more complicated, thus improving the hardware and software development and maintenance costs.
  • the remote upgrade speed of the system is slow.
  • the remote connection of the image signal source of the ARM architecture is mainly based on the Ethernet function of ARM. Especially in the process of remote upgrade of the FPGA program, the program file must be sent to the ARM through the Ethernet. ARM writes the file to the FLASH of the FPGA through the serial bus, and the whole upgrade process takes a relatively slow time.
  • the purpose of the present invention is to solve the deficiencies of the above background art, and to provide a simple structure and low cost.
  • a soft processor-based image signal source that outputs an image signal with high efficiency and a method of processing the image signal.
  • a soft processor-based image signal source comprising an output interface and a first soft processor, a protocol stack and a main control block disposed in a programmable logic device;
  • the programmable logic device is configured to convert the image file into an image signal output according to the configuration information of the upper computer;
  • the protocol stack is configured to receive the configuration information and the image file sent by the host computer
  • the first soft processor is configured to configure the main control block according to the configuration information
  • the main control block is configured to process the image file according to a configuration command of the first soft processor, and output the image signal to the output interface.
  • the foregoing solution further includes an Ethernet transceiver module and an external data storage module; wherein
  • An Ethernet transceiver module is configured to implement communication between the programmable logic device and the host computer;
  • An external data storage module is configured to store the configuration information and the image file.
  • the foregoing solution further includes a complex programmable logic module and a non-volatile storage module; the protocol stack in the foregoing solution is further configured to receive a program file sent by the host computer, and a program configuration or an upgrade instruction;
  • a complex programmable logic module is used to implement program configuration or upgrade of the programmable logic device
  • a non-volatile memory module is used to store program files that implement program configuration or upgrade of the programmable logic device.
  • the present invention also provides a soft processor-based image signal processing method, including the following steps:
  • the protocol stack receives configuration information and an image file sent by the host computer
  • the first soft processor configures the main control block according to the configuration information
  • the main control block processes the image file according to a configuration command of the first soft processor to generate an image signal.
  • the foregoing solution further includes the step of: completing configuration of an interface type of the output interface according to the configuration command of the first soft processor.
  • the foregoing solution further includes a program configuration or an upgrade method, including the following steps:
  • the first soft processor sends a control instruction to the complex programmable logic module according to the program configuration or upgrade instruction;
  • the protocol stack receives the program file sent by the host computer and caches the program file
  • the complex programmable logic module reads the cached program file according to the control instruction to complete the program configuration or upgrade operation of the programmable logic device.
  • the image signal source of the invention adopts a single FPGA (programmable logic device) mode, and a soft processor is embedded therein to realize image signal processing function, and an image program source upgrade program management and FPGA loading are implemented by using CPLD (complex programmable logic module).
  • the startup function eliminates the ARM architecture and reduces the complicated process of processing data based on the ARM architecture signal source, which makes the system remote upgrade fast, the online and offline output image mode has high transmission efficiency, and the image switching speed is fast; and based on the soft processor architecture
  • the signal source system has a simple architecture, low hardware cost, and low software development and maintenance costs.
  • Figure 1 is a block diagram of the circuit of the present invention.
  • FIG. 3 is a flow chart of the online image signal output of the present invention.
  • the programmable logic device 3 is implemented based on the FPGA
  • the complex programmable logic module 5 is implemented based on the CPLD
  • the embedded memory control block is implemented based on the eMMC (eMMC flash embedded memory) memory.
  • the lossless memory module 6 is implemented based on Nand (Nand flash memory) flash memory.
  • the image signal source based on the soft processor of the present invention comprises an Ethernet transceiver module 2, a programmable logic device 3, an external data storage module 4, a complex programmable logic module 5, a Nand storage module 6 and an output interface 7. .
  • the connection relationship between the two is: the input control end of the Ethernet transceiver module 2 is connected to the upper computer 1, and the output control end of the Ethernet transceiver module 2 is connected to the input control end of the programmable logic device 3;
  • the data control end of the device 3 is connected to the input end of the external data storage module 4.
  • the image output end of the programmable logic device 3 is connected to the input end of the output interface 7, and the interface control end of the programmable logic device 3 is complexly programmable.
  • An input end of the logic module 5, the configuration input end of the programmable logic device 3 is connected to the data output end of the complex programmable logic module 5; the data control end of the complex programmable logic module 5 is connected to the input end of the Nand memory module 6 .
  • the programmable logic device 3 includes a first soft processor 31, a protocol stack 32, a main control block 33, an eMMC storage control block 34, a DDR (DDR SDRAM Double Rate Synchronous Dynamic Random Access Memory) cache control block 35, and an image.
  • An output control block 36 ; an input control end of the protocol stack 32 is connected to the host computer 1, a command output end of the protocol stack 32 is connected to an input end of the first soft processor 31, and an output control terminal of the protocol stack 32 is mainly controlled.
  • the control end of the first soft processor 31 is connected to the command control end of the main control block 33; the storage data control end of the main control block 33 is connected to the input end of the eMMC storage control block 34.
  • the buffer data control end of the main control block 33 is connected to the input end of the DDR buffer control block 35, the output end of the main control block 33 is connected to the input end of the image output control block 36; the output end of the image output control block 36 is output.
  • the programmable logic device 3 further includes a main external storage interface control block 37 and a configuration module 38.
  • the interface control end of the main control block 33 is connected to the input end of the main external storage interface control block 37, and the main external storage
  • the output of the interface control block 37 is coupled to the input of the complex programmable logic module 5; the input of the configuration module 38 is coupled to the data output of the complex programmable logic module 35.
  • the external data storage module 4 includes an eMMC external storage module 41 and an DDR external cache module 42.
  • the input end of the eMMC external storage module 41 is connected to the output end of the eMMC storage control block 34, and the DDR external cache module 42 The input is connected to the output of the DDR buffer control block 35.
  • the output interface 7 includes a first output interface 71, a second output interface 72, a third output interface 73, and a fourth output interface 74, the first output interface 71, the second output interface 72, and the third output interface.
  • the inputs of 73 and fourth output interface 74 are coupled to the four outputs of image output control block 36, respectively.
  • the complex editable logic module 5 includes an external storage interface control block 51, a second soft processor 52, a Nand storage control block 53 and a load module 54; the input connection from the external storage interface control block 51 can be
  • the interface control terminal of the programming logic device 3 is connected to the input end of the second soft processor 52, and the data output terminal of the external storage interface control block 51 is connected to the Nand storage control.
  • the control end of the second soft processor 52 is connected to the command control end of the Nand storage control block 53, and the data control end of the Nand storage control block 53 is connected to the input end of the Nand storage module 6.
  • the data output terminal of the Nand memory control block 53 is connected to the input terminal of the load module 54.
  • the output terminal of the load module 54 is connected to the configuration input terminal of the programmable logic device 3.
  • each control logic module is as follows:
  • the host computer (PC) 1 is used for human-computer interaction, editing of signal source image output parameters and image output control, and remote upgrade.
  • the Ethernet transceiver module 2 is configured to receive data sent from the host computer to the programmable logic device, and receive data sent from the programmable logic device to the host computer.
  • FPGA Programmable Logic Device
  • First soft processor (nios ii A) 31 The main function is responsible for task scheduling, file system management, analysis and distribution of control commands, and workflow control for each control block within the programmable logic device.
  • Protocol stack 32 Ethernet transport protocol layer, parses data transmitted by Ethernet, commands data transmission to nios ii A, and transmits image files to the main control block.
  • the main control block 33 mainly performs large data volume transmission, bus switching and multiplexing; specifically, processes the image file according to the control command of the first soft processor, and outputs the image file to the output interface.
  • the eMMC storage control block 34 performs data interaction with the main control block, and performs read and write access to the eMMC external storage module.
  • eMMC external storage module 41 an external storage unit, mainly used to store configuration information and image files;
  • DDR cache control block 35 mainly performs data interaction with the main control block, and performs read and write access to the DDR external cache module.
  • DDR external cache module 42 an external data buffer unit, mainly used to store the number of systems to be processed at zero time according to.
  • the image output control block 36 mainly performs data interaction with the main control block, and sets different output interface types and output image files differently for the external output interface.
  • the main external storage interface control block 37 mainly performs data interaction with the main control block, and controls the external bus to perform data transmission with the CPLD.
  • Configuration module 38 configured to program the programmable logic device according to the upgrade program sent by the complex programmable logic module to complete the start of the programmable logic device, belonging to the hardware logic configuration inside the programmable logic device, and the programmable logic device is first configured After the module is configured, it can enter the initialization state before it can enter the user state. After entering the user state, the user operation can be performed.
  • the first output interface 71 mainly provides an image output interface of an LVDS interface type, and the interface supports an LVDS interface type of 1link/2link/4link/8link.
  • the second output interface 72 mainly provides an image output interface of the MIPI interface type, and the interface supports the MIPI DSI interface type of 4lane/8lane.
  • the third output interface 73 mainly provides an image output interface of the DP interface type, and the interface supports the DP1.2 interface type of 4lane/8lane.
  • the fourth output interface 74 mainly provides an image output interface of the V-BY-ONE interface type, and the interface supports the V-BY-ONE interface type of 8lane/16lane.
  • CPLD Complex Programmable Logic Module
  • Second soft processor (nios ii B) 52 used to handle task scheduling, command parsing, and workflow control within the CPLD.
  • the Nand storage control block 53 is configured to receive data from the external storage interface control block, store it in an external Nand storage module, and read data from the external Nand storage module to the loading module: receiving from the second Control commands for soft processors.
  • the loading module 54 is configured to receive an upgrade program of the programmable logic device from the Nand memory control block, and program the programmable logic device through an external bus.
  • Nand memory module 6 A memory controller outside the CPLD that holds the program files of the programmable logic device.
  • the image signal source based on the soft processor adopts a single programmable logic device, and the nios ii soft processor is embedded internally to realize the function of the image signal source.
  • the main processing signals include remote program configuration or upgrade operation, online image signal output operation, Online download image information operation, offline image signal output operation.
  • the host computer 1 sends a program configuration or upgrade command to the protocol stack 32 through the Ethernet transceiver module 2, and the protocol stack 32 sends the received program configuration or upgrade command to the first soft processor 31, and the first soft processor 31 receives After the program configuration or upgrade command, the program configuration or upgrade command is sent to the second soft processor 52 in the complex editable logic module 5 by the control main control block 33 and the main external storage interface control block 37.
  • the host computer 1 sends the configuration program or the upgrade program file of the image signal source to the protocol stack 32 for parsing through the Ethernet transceiver module 2, and the protocol stack 32 passes the parsed program file through the main control block 33 and the DDR cache control block 35. Saved to the DDR external cache module 42.
  • the control main control block 33 and the DDR cache control block 35 read the program file from the DDR external cache module 42 and send it to the complex through the main external storage interface control block 37.
  • the second soft processor 52 receives the program file received from the external storage interface control block 51 according to the program configuration or the upgrade command, and stores the program file in the Nand storage module 6 through the Nand storage control block 53.
  • the complex programmable logic module 5 After the image source is powered up next time, the complex programmable logic module 5 first performs self-starting.
  • the second soft processor 52 inside the CPLD controls the Nand storage control block 53 to read the corresponding from the Nand storage module 6 according to the startup program configuration of the programmable logic device 3, that is, the program configuration or the upgrade instruction.
  • the configuration program or upgrade program file is sent to the load module 54.
  • the loading module 54 sends the program file to the configuration module 38 of the programmable logic device 3 through the external bus. After receiving the program file, the configuration module 38 performs program configuration of the programmable logic device to complete the program configuration or upgrade operation.
  • the host computer 1 transmits configuration information and an image file to the protocol stack 32 through the Ethernet transceiver module 2 for parsing.
  • the protocol stack 32 sends the parsed configuration information to the first soft processor 31.
  • the first soft processor 31 configures the function switching of the main control block 33 according to the received configuration information, and sets the image output control block 36 to select the output interface type. Control the coordinated work of each logic block.
  • the protocol stack 32 sends the parsed image file to the main control block 33.
  • the main control block 33 sends the image file to the DDR cache control block 35, through the DDR.
  • the cache control block 35 writes the image file into the DDR external cache module 42.
  • the host computer 1 sends an image output command to the first soft processor 31, and the first soft processor 31 controls the main control block 33 and the DDR cache control block 35 from the DDR external cache module 42 according to the received command.
  • the image file is read and sent to the image output control block 36.
  • the image output control block 36 performs the same image output or different image output display through the configured output interface; when the first soft processor 31 receives the image switching command, The image output control block 36 reads different image files from the DDR external buffer module 35 according to the command, and performs output display; if no image switching command is received, the current screen output display is maintained.
  • offline image signal output operation is divided into online download and offline output two parts, online download is sent by the host computer to send image files and configuration information to the storage area outside the programmable logic device (eMMC external storage module) Then, after the next time the image signal source is powered off offline, the image file is read and output through the corresponding interface, as shown in FIG. 4, the specific process is:
  • the host computer 1 transmits configuration information and an image file to the protocol stack 32 through the Ethernet transceiver module 2 for parsing.
  • the protocol stack 32 sends the parsed configuration information and the image file to the main control block 33.
  • the main control block 33 After receiving the configuration information and the image file, the main control block 33 sends the configuration information and the image file to the DDR cache control block 35, and the configuration information is transmitted through the DDR cache control block 35. And the image file is written to the DDR external cache module 42.
  • the first soft processor 31 controls the main control block 33 and the DDR buffer control block 35 to read configuration information and image files from the DDR external cache module 42 and send them to the eMMC storage control block 34, which will configure the information. And the image file is saved to the eMMC external storage module 41 for online download.
  • the first soft processor 31 reads the configuration information from the eMMC external storage module 41 by controlling the main control block 33 and the eMMC storage control block 34, and sends it to the DDR cache control block 35 for saving.
  • the main control block 33 controls the DDR cache control block 35 to read configuration information from the DDR external cache module 42 for transmission to the first soft processor 31.
  • the first soft processor 31 configures the function switching of the main control block 33 according to the configuration information, and the configuration image output control block 36 selects the output interface type.
  • the main control block 33 controls the eMMC storage control block 34 to read the image file from the eMMC external storage module 41, and sends it to the DDR cache control block 35 for storage in the DDR external cache module 42.
  • the main control block 33 controls the DDR buffer control block 35 to read the image file from the DDR external buffer module 42 and send it to the image output control block 36.
  • the image output control block 36 performs the same image output or different images through the configured output interface. The output is displayed.

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Abstract

公开了一种基于软处理器的图像信号源及其处理图像信号的方法。它包括用于完成图像信号输出、同上位机进行通信的可编程逻辑器件，用于与可编程逻辑器件进行通信完成程序升级、给可编程逻辑器件发送升级程序的复杂可编程逻辑模块和用于对可编程逻辑器件输出的图像文件提供不同的图像输出接口类型的输出接口，所述可编程逻辑器件包括第一软处理器、协议栈和主控制块。图像信号源采用单FPGA的方式，内部嵌入软处理器来实现图像信号处理功能，采用CPLD实现图像信号源的升级程序管理和FPGA的加载启动功能，具有系统架构简单、成本低，系统远程升级速度快，在线、离线输出图像模式传输效率高，图像切换速度快的优点。

Description

一种基于软处理器的图像信号源及其处理图像信号的方法 技术领域
本发明属于图像信号源技术领域，具体涉及一种基于软处理器的图像信号源及其处理图像信号的方法。
背景技术
目前的图像信号源是基于硬处理器(ARM)协同可编程逻辑器件(FPGA)来实现的，基于ARM的图像信号源存在以下缺陷：
1、上电输出第一幅图像时间长，由于ARM架构的信号源图像数据都保存在ARM外围的flash中，所以上电后，ARM要先启动，启动完成后从flash中读出图像数据到ARM的DDR中，再从ARM的DDR中读取数据通过互联总线传速到FPGA的DDR中，FPGA内部控制逻辑块再从FPGA的DDR中读出图像数据输出到图像输出接口，整个处理过程复杂，造成首次上电输出第一幅图时间过长。
2、图像数据传输效率低，无论是在线输出图像信号还是离线输出图像信号，图像信号首先通过ARM处理，ARM处理完成后再通过互联总线的方式传输给FPGA，然后FPGA在根据图像信号输出的类型进行处理后通过不同接口输出，整个处理过程比较繁琐，造成图像信号输出效率过低。
3、架构复杂成本高，ARM架构的图像信号源需要采用ARM加上FPGA来共同完成，造成硬件架构和软件架构都比较复杂，从而提高了硬件和软件开发、维护成本。
4、系统的远程升级速度慢，ARM架构的图像信号源对外的远程连接主要依据ARM的以太网功能，尤其是在进行FPGA程序的远程升级过程中，要先将程序文件通过以太网发送给ARM，ARM在将文件通过串行总线写到FPGA的FLASH中，整个升级过程时间比较慢。
发明内容
本发明的目的就是为了解决上述背景技术存在的不足，提供一种结构简单、成本低、 输出图像信号效率高的基于软处理器的图像信号源及其处理图像信号的方法。
本发明采用的技术方案是：一种基于软处理器的图像信号源，包括输出接口以及设置于一颗可编程逻辑器件中的第一软处理器、协议栈和主控制块；其中，
可编程逻辑器件用于根据上位机的配置信息将图像文件转换成图像信号输出；
协议栈用于接收上位机发送的所述配置信息和所述图像文件；
第一软处理器用于根据所述配置信息对主控制块进行配置；
主控制块用于根据所述第一软处理器的配置命令对所述图像文件进行处理，输出所述图像信号至所述输出接口。
进一步地，上述方案还包括以太网收发模块和外部数据存储模块；其中，
以太网收发模块用于实现所述可编程逻辑器件和所述上位机的通信；
外部数据存储模块用于存储所述配置信息和所述图像文件。
进一步地，上述方案还包括复杂可编程逻辑模块和非易失性存储模块；上述方案中的协议栈还用于接收上位机发送的程序文件以及程序配置或升级指令；其中，
复杂可编程逻辑模块用于实现所述可编程逻辑器件的程序配置或升级；
非易失性存储模块用于存储实现所述可编程逻辑器件的程序配置或升级的程序文件。
此外，本发明还提供一种基于软处理器的图像信号处理方法，包括以下步骤：
(1)协议栈接收上位机发送的配置信息和图像文件；
(2)第一软处理器根据所述配置信息对主控制块进行配置；
(3)所述主控制块根据所述第一软处理器的配置命令对所述图像文件进行处理生成图像信号。
进一步地，上述方案还包括以下步骤：根据所述第一软处理器的配置命令完成输出接口的接口类型的配置。
进一步地，上述方案还包括程序配置或升级方法，包括以下步骤：
(s1)协议栈接收上位机发送的程序配置或升级指令；
(s2)第一软处理器根据所述程序配置或升级指令向复杂可编程逻辑模块发送控制指令；
(s3)协议栈接收上位机发送的程序文件并将所述程序文件进行缓存；
(s4)复杂可编程逻辑模块根据所述控制指令读取缓存处理后的程序文件完成可编程逻辑器件的程序配置或升级操作。
本发明图像信号源采用单FPGA(可编程逻辑器件)的方式，内部嵌入软处理器来实现图像信号处理功能，采用CPLD(复杂可编程逻辑模块)实现图像信号源的升级程序管理和FPGA的加载启动功能，省却了ARM架构，减少了基于ARM架构信号源处理数据复杂的过程，使得系统远程升级速度快，在线、离线输出图像模式传输效率高，图像切换速度快；并且基于软处理器架构的信号源系统架构简单，硬件成本低，软件开发和维护成本也比较低。
附图说明
图1为本发明的电路框图。
图2为本发明远程升级启动的流程图。
图3为本发明在线图像信号输出的流程图。
图4为本发明离线图像信号输出的流程图。
图中：1-上位机；2-以太网收发模块；3-可编程逻辑器件；31-第一软处理器；32-协议栈；33-主控制块；34-嵌入式存储控制块；35-DDR缓存控制块；36-图像输出控制块；37-主外部存储接口控制块；38-配置模块；4-外部存储模块；41-嵌入式存储模块；42-DDR缓存模块；5-复杂可编程逻辑模块；51-从外部存储接口控制块；52-非易失性存储控制块；53-第二软处理器；54-加载模块；6-非易失性存储模块；7-输出接口；71-第一输出接口；72-第二输出接口；73-第三输出接口；74-第四输出接口。
具体实施方式
下面结合附图和具体实施例对本发明作进一步的详细说明，便于清楚地了解本发明，但它们不对本发明构成限定。
本实施例可编程逻辑器件3基于FPGA实现、复杂可编程逻辑模块5基于CPLD实现、嵌入式存储控制块基于eMMC(eMMC flash内嵌式记忆体)存储器实现、非易 失性存储模块6基于Nand(Nand flash快闪记忆体)闪存实现。
如图1所示，本发明基于软处理器的图像信号源包括以太网收发模块2、可编程逻辑器件3、外部数据存储模块4、复杂可编程逻辑模块5、Nand存储模块6和输出接口7。其各自之间的连接关系为：以太网收发模块2的输入控制端连接上位机1，所述以太网收发模块2的输出控制端连接可编程逻辑器件3的输入控制端；所述可编程逻辑器件3的数据控制端连接外部数据存储模块4的输入端，所述可编程逻辑器件3的图像输出端连接输出接口7的输入端，所述可编程逻辑器件3的接口控制端连接复杂可编程逻辑模块5的输入端，所述可编程逻辑器件3的配置输入端连接复杂可编程逻辑模块5的数据输出端；所述复杂可编程逻辑模块5的数据控制端连接Nand存储模块6的输入端。
上述方案中，可编程逻辑器件3包括第一软处理器31、协议栈32、主控制块33、eMMC存储控制块34、DDR(DDR SDRAM双倍速率同步动态随机存储器)缓存控制块35和图像输出控制块36；所述协议栈32的输入控制端连接上位机1，所述协议栈32的命令输出端连接第一软处理器31的输入端，所述协议栈32的输出控制端主控制块33的输入控制端；所述第一软处理器31的控制端连接主控制块33的命令控制端；所述主控制块33的存储数据控制端连接eMMC存储控制块34的输入端，所述主控制块33的缓存数据控制端连接DDR缓存控制块35的输入端，所述主控制块33的输出端连接图像输出控制块36的输入端；所述图像输出控制块36的输出端输出接口7的输入端。
上述方案中，可编程逻辑器件3还包括主外部存储接口控制块37和配置模块38，所述主控制块33的接口控制端连接主外部存储接口控制块37的输入端，所述主外部存储接口控制块37的输出端连接复杂可编程逻辑模块5的输入端；所述配置模块38的输入端连接复杂可编程逻辑模块35的数据输出端。
上述方案中，外部数据存储模块4包括eMMC外部存储模块41和DDR外部缓存模块42，所述eMMC外部存储模块41的输入端连接eMMC存储控制块34的输出端，所述DDR外部缓存模块42的输入端连接DDR缓存控制块35的输出端。
上述方案中，输出接口7包括第一输出接口71、第二输出接口72、第三输出接口73和第四输出接口74，所述第一输出接口71、第二输出接口72、第三输出接口73和第四输出接口74的输入端分别连接图像输出控制块36的四个输出端。
上述方案中，复杂可编辑逻辑模块5包括从外部存储接口控制块51、第二软处理器52、Nand存储控制块53和加载模块54；所述从外部存储接口控制块51的输入端连接可编程逻辑器件3的接口控制端，所述从外部存储接口控制块51的命令输出端连接第二软处理器52的输入端，所述从外部存储接口控制块51的数据输出端连接Nand存储控制块53的数据输入端，所述第二软处理器52的控制端连接Nand存储控制块53的命令控制端，所述Nand存储控制块53的数据控制端连接Nand存储模块6的输入端，所述Nand存储控制块53的数据输出端连接加载模块54的输入端，所述加载模块54的输出端连接可编程逻辑器件3的配置输入端。
上述方案中，各控制逻辑模块的作用分别如下：
上位机(PC)1用于人机交互、编辑信号源图像输出参数和图像输出的控制、远程升级。
以太网收发模块2，用于接收来自上位机的数据发送给可编程逻辑器件、接收来自可编程逻辑器件的数据发送给上位机。
可编程逻辑器件(FPGA)3：为整个系统的核心部件，内部集成软处理器(nios ii A)和各自定义功能模块完成图像信号输出、同上位机进行通信。
第一软处理器(nios ii A)31：主要功能负责可编程逻辑器件内部各控制块的任务调度、文件系统管理、控制命令的解析和分发以及工作流程控制。
协议栈32：以太网传输协议层，解析以太网传输的数据，命令数据传输给nios ii A，图像文件传输给主控制块。
主控制块33：主要进行大数据量传输，总线的切换和复用；具体用于根据第一软处理器的控制命令对图像文件进行处理、输出图像文件至输出接口。
eMMC存储控制块34：主要同主控制块进行数据交互，对eMMC外部储存模块进行读写访问。
eMMC外部存储模块41：外部存储单元，主要用来存储配置信息和图像文件；
DDR缓存控制块35：主要同主控制块进行数据交互，对DDR外部缓存模块进行读写访问。
DDR外部缓存模块42：外部的数据缓存单元，主要用来零时存放系统待处理的数 据。
图像输出控制块36：主要同主控制块进行数据交互，针对外部输出接口不同设置不同的输出接口类型、输出图像文件。
主外部存储接口控制块37：主要同主控制块进行数据交互，控制外部总线同CPLD进行数据传输。
配置模块38：用于根据复杂可编程逻辑模块发送的升级程序对可编程逻辑器件进行程序配置完成可编程逻辑器件的启动，属于可编程逻辑器件内部的硬件逻辑配置，可编程逻辑器件首先由配置模块配置后，才能进入初始化状态，然后才能进入用户状态，进入用户状态后才能执行用户操作。
第一输出接口71：主要提供LVDS接口类型的图像输出接口，接口支持1link/2link/4link/8link的LVDS接口类型。
第二输出接口72：主要提供MIPI接口类型的图像输出接口，接口支持4lane/8lane的MIPI DSI接口类型。
第三输出接口73：主要提供DP接口类型的图像输出接口，接口支持4lane/8lane的DP1.2接口类型。
第四输出接口74：主要提供V-BY-ONE接口类型的图像输出接口，接口支持8lane/16lane的V-BY-ONE接口类型。
复杂可编程逻辑模块(CPLD)5：外部挂载存储器用来存储可编程逻辑器件3的程序文件，同可编程逻辑器件3进行通信完成程序升级，给可编程逻辑器件进行程序配置完成可编程逻辑器件的启动。
从外部存储接口控制块51：用于同可编程逻辑器件进行总线交互，接收来自可编程逻辑器件的配置程序和命令数据，配置程序转发给Nand存储控制块，命令数据转发给第二软处理器。
第二软处理器(nios ii B)52：用来处理CPLD内部的任务调度、命令解析和工作流程控制。
Nand存储控制块53：用于接收来自从外部存储接口控制块的数据，存储到外部的Nand存储模块中，从外部的Nand存储模块中读取数据发送给加载模块：接收来自第二 软处理器的控制命令。
加载模块54：用来接收来自Nand存储控制块的可编程逻辑器件的升级程序，通过外部总线对可编程逻辑器件进行程序配置。
Nand存储模块6：CPLD外的存储控制器，用来保存可编程逻辑器件的程序文件。
基于软处理器的图像信号源采用单可编程逻辑器件的方式，内部嵌入nios ii软处理器来实现图像信号源的功能，主要处理信号操作包括远程程序配置或升级操作、在线图像信号输出操作、在线下载图像信息操作、离线图像信号输出操作。
1、远程程序配置或升级操作，如图2所示，操作过程为：
1.1)搭建环境，图像信号源和上位机进行连接。
1.2)上位机1通过以太网收发模块2向协议栈32发送程序配置或升级指令，协议栈32将接收的程序配置或升级指令发送到第一软处理器31，第一软处理器31接收到程序配置或升级指令后，通过控制主控制块33和主外部存储接口控制块37向复杂可编辑逻辑模块5中的第二软处理器52发送程序配置或升级指令。
1.3)上位机1将图像信号源的配置程序或升级程序文件通过以太网收发模块2发送给协议栈32进行解析，协议栈32将解析后的程序文件经过主控制块33和DDR缓存控制块35保存到DDR外部缓存模块42中。
1.4)第一软处理器31收到程序保存完成后，控制主控制块33和DDR缓存控制块35将程序文件从DDR外部缓存模块42读出，通过主外部存储接口控制块37发送给复杂可编辑逻辑模块5中的从外部存储接口控制块51。
1.5)第二软处理器52根据程序配置或升级指令控制从外部存储接口控制块51接收程序文件，通过Nand存储控制块53将程序文件存储到Nand存储模块6中。
1.6)下次图像信号源上电后，复杂可编程逻辑模块5先进行自启动。
1.7)CPLD启动完成后，CPLD内部的第二软处理器52会根据可编程逻辑器件3的启动程序配置即程序配置或升级指令，控制Nand存储控制块53从Nand存储模块6中读取相应的配置程序或升级程序文件，发送给加载模块54。
1.8)加载模块54将程序文件通过外部总线的方式发送给可编程逻辑器件3的配置模块38，配置模块38接收到程序文件后，进行可编程逻辑器件的程序配置，完成程序配置或升级操作。
2、在线图像信号输出操作，如图3所示，操作过程为：
2.1)搭建环境，将图像信号源和PC进行连接，打开图像信号源。
2.2)打开上层应用软件，选择在线图像输出操作，针对输出接口类型选择相应的模组信息，点击开始。
2.3)上位机1通过以太网收发模块2向协议栈32发送配置信息和图像文件进行解析。
2.4)协议栈32将解析的配置信息发送到第一软处理器31，第一软处理器31根据接收到的配置信息配置主控制块33的功能切换、设置图像输出控制块36选择输出接口类型，控制各逻辑块的协同工作。
2.5)第一软处理器31信息配置完成后，协议栈32将解析的图像文件发送到主控制块33，主控制块33接收到图像文件后将图像文件发送给DDR缓存控制块35，通过DDR缓存控制块35将图像文件写入到DDR外部缓存模块42中。
2.6)图像文件保存完成后，上位机1发送图像输出命令至第一软处理器31，第一软处理器31根据接收的命令控制主控制块33和DDR缓存控制块35从DDR外部缓存模块42中读取图像文件，发送给图像输出控制块36，图像输出控制块36通过配置的输出接口进行同一幅图像输出或者不同图像输出显示；当第一软处理器31接收到图像切换命令时，则根据命令的不同控制图像输出控制块36从DDR外部缓存模块35中读取不同的图像文件，进行输出显示；如果没有接收到图像切换命令，则保持当前画面输出显示。
3、离线图像信号输出操作：离线输出操作分为在线下载和离线输出两部分，在线下载即通过上位机下发图像文件和配置信息存储到可编程逻辑器件外部的存储区(eMMC外部存储模块)，然后在下次图像信号源离线开电的情况下再读取图像文件通过相应的接口进行输出，如图4所示，具体过程为：
3.1)搭建环境，图像信号源和上位机进行连接，打开图像信号源。
3.2)打开上层应用软件，选择下载图像信息操作，针对输出接口类型选择相应的模 组信息，点击开始。
3.3)上位机1通过以太网收发模块2向协议栈32发送配置信息和图像文件进行解析。
3.4)协议栈32将解析的配置信息和图像文件发送到主控制块33，主控制块33接收到配置信息和图像文件后，发送给DDR缓存控制块35，通过DDR缓存控制块35将配置信息和图像文件写入到DDR外部缓存模块42中。
3.5)第一软处理器31控制主控制块33和DDR缓存控制块35从DDR外部缓存模块42中读取配置信息和图像文件，发送给eMMC存储控制块34，eMMC存储控制块34将配置信息和图像文件保存到eMMC外部存储模块41中，实现在线下载。
3.6)在下次图像信号源单独上电后，第一软处理器31通过控制主控制块33和eMMC存储控制块34从eMMC外部存储模块41中读取配置信息，发送给DDR缓存控制块35保存到DDR外部缓存模块42中，主控制块33再控制DDR缓存控制块35从DDR外部缓存模块42中读取配置信息发送至第一软处理器31。
3.7)第一软处理器31根据配置信息配置主控制块33的功能切换、配置图像输出控制块36选择输出接口类型。
3.8)配置完成后，主控制块33控制eMMC存储控制块34从eMMC外部存储模块41中读取图像文件，发送给DDR缓存控制块35保存到DDR外部缓存模块42中。
3.9)主控制块33控制DDR缓存控制块35从DDR外部缓存模块42中读取图像文件，发送给图像输出控制块36，图像输出控制块36通过配置的输出接口进行同一幅图像输出或者不同图像输出显示。
本说明书中未作详细描述的内容属于本领域专业技术人员公知的现有技术。

Claims (10)

  1. 一种基于软处理器的图像信号源，其特征在于，包括输出接口(7)以及设置于一颗可编程逻辑器件(3)中的第一软处理器(31)、协议栈(32)和主控制块(33)；其中，
    所述可编程逻辑器件(3)用于根据上位机的配置信息将图像文件转换成图像信号输出；
    所述协议栈(32)用于接收上位机发送的所述配置信息和所述图像文件；
    所述第一软处理器(31)用于根据所述配置信息对主控制块(33)进行配置；
    所述主控制块(33)用于根据所述第一软处理器(31)的配置命令对所述图像文件进行处理，输出所述图像信号至所述输出接口(7)。
  2. 根据权利要求1所述的一种基于软处理器的图像信号源，其特征在于，还包括：
    以太网收发模块(2)，用于实现所述可编程逻辑器件(3)和所述上位机的通信；
    外部数据存储模块(4)，用于存储所述配置信息和所述图像文件。
  3. 根据权利要求2所述的一种基于软处理器的图像信号源，其特征在于，所述外部数据存储模块(4)包括嵌入式存储模块(41)和DDR缓存模块(42)，所述可编程逻辑器件(3)还包括嵌入式存储控制块(34)、DDR缓存控制块(35)和图像输出控制块(36)；
    所述嵌入式存储模块(41)用于存储所述配置信息和所述图像文件；
    所述DDR缓存模块(42)用于临时存放所述配置信息和所述图像文件；
    所述嵌入式存储控制块(34)用于对所述嵌入式存储模块(41)进行读写访问；
    所述DDR缓存控制块(35)用于对所述DDR缓存模块(42)进行读写访问；
    所述图像输出控制块(36)用于根据所述第一软处理器(31)的配置命令完成所述输出接口(7)的接口类型的配置。
  4. 根据权利要求1所述的一种基于软处理器的图像信号源，其特征在于，还包括复杂可编程逻辑模块(5)和非易失性存储模块(6)；所述协议栈(32)还用于接收上位机发送的程序文件以及程序配置或升级指令；
    所述复杂可编程逻辑模块(5)用于实现所述可编程逻辑器件(3)的程序配置或升 级；
    所述非易失性存储模块(6)，用于存储实现所述可编程逻辑器件(3)的程序配置或升级的程序文件。
  5. 根据权利要求4所述的一种基于软处理器的图像信号源，其特征在于，所述可编程逻辑器件(3)还包括：
    主外部存储接口控制块(37)，用于与所述主控制块(33)进行数据交互，控制外部总线与所述复杂可编程逻辑模块(5)进行数据传输；
    配置模块(38)，用于根据所述复杂可编程逻辑模块(5)发送的所述程序文件对所述可编程逻辑器件(3)进行程序配置或升级。
  6. 根据权利要求5所述的一种基于软处理器的图像信号源，其特征在于，所述复杂可编程逻辑模块(5)包括：
    从外部存储接口控制块(51)，用于接收所述程序文件以及程序配置或升级指令；
    第二软处理器(52)，用于根据所述程序配置或升级指令控制所述从外部存储接口控制块(51)和非易失性存储控制块(53)的工作流程；
    非易失性存储控制块(53)，用于将所述程序文件存储到所述非易失性存储模块(6)中，以及从所述非易失性存储模块(6)中读取所述程序文件发送给加载模块(54)；
    加载模块(54)，用于接收来自所述非易失性存储控制块(53)的程序文件，并通过外部总线发送给所述可编程逻辑器件(3)。
  7. 一种基于软处理器的图像信号处理方法，其特征在于，包括以下步骤：
    (1)协议栈(32)接收上位机(1)发送的配置信息和图像文件；
    (2)第一软处理器(31)根据所述配置信息对主控制块(33)进行配置；
    (3)所述主控制块(33)根据所述第一软处理器(31)的配置命令对所述图像文件进行处理生成图像信号。
  8. 根据权利要7所述的一种基于软处理器的图像信号处理方法，其特征在于，还包括以下步骤：根据所述第一软处理器(31)的配置命令完成输出接口(7)的接口类型的配置。
  9. 根据权利要求7所述的一种基于软处理器的图像信号处理方法，其特征在于，还包括程序配置或升级方法，包括以下步骤：
    (s1)协议栈(32)接收上位机(1)发送的程序配置或升级指令；
    (s2)第一软处理器(31)根据所述程序配置或升级指令向复杂可编程逻辑模块(5)发送控制指令；
    (s3)协议栈(32)接收上位机(1)发送的程序文件并将所述程序文件进行缓存；
    (s4)复杂可编程逻辑模块(5)根据所述控制指令读取缓存处理后的程序文件完成可编程逻辑器件(3)的程序配置或升级操作。
  10. 根据权利要求9所述的一种基于软处理器的图像信号处理方法，其特征在于，步骤s4具体包括以下步骤：
    (s4.1)第二软处理器(52)根据所述控制指令控制从外部存储接口控制块(51)接收程序文件，通过非易失性存储控制块(53)将程序文件存储到非易失性存储模块(6)；
    (s4.2)在图像信号源上电后，复杂可编辑逻辑模块(5)先自启动，第二软处理器(52)控制非易失性存储控制块(53)从非易失性存储模块(6)读取程序文件，发送给加载模块(54)；
    (s4.3)加载模块(54)将程序文件通过外部总线发送给可编程逻辑器件的配置模块(38)，配置模块(38)接收到程序文件后，进行可编程逻辑器件(3)的程序配置，完成程序配置或升级操作。
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