KR20170084043A - 멀티­채널 ｉ²ｓ 송신 제어 시스템 및 방법 - Google Patents

멀티­채널 ｉ²ｓ 송신 제어 시스템 및 방법 Download PDF

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Publication number
KR20170084043A
KR20170084043A KR1020177011445A KR20177011445A KR20170084043A KR 20170084043 A KR20170084043 A KR 20170084043A KR 1020177011445 A KR1020177011445 A KR 1020177011445A KR 20177011445 A KR20177011445 A KR 20177011445A KR 20170084043 A KR20170084043 A KR 20170084043A
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KR
South Korea
Prior art keywords
bits
memory line
bit
read
memory
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KR1020177011445A
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English (en)
Korean (ko)
Inventor
제임스 캐서디
로드니 페사벤토
세르게이 파블로프
Original Assignee
마이크로칩 테크놀로지 인코포레이티드
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Publication of KR20170084043A publication Critical patent/KR20170084043A/ko
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Communication Control (AREA)
  • Information Transfer Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Multi Processors (AREA)
  • Bus Control (AREA)
KR1020177011445A 2014-11-11 2015-11-09 멀티­채널 ｉ²ｓ 송신 제어 시스템 및 방법 Withdrawn KR20170084043A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/538,133 US9842071B2 (en) 2014-11-11 2014-11-11 Multi-channel I2S transmit control system and method
US14/538,133 2014-11-11
PCT/US2015/059661 WO2016077189A1 (en) 2014-11-11 2015-11-09 Multi-channel i2s transmit control system and method

Publications (1)

Publication Number Publication Date
KR20170084043A true KR20170084043A (ko) 2017-07-19

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020177011445A Withdrawn KR20170084043A (ko) 2014-11-11 2015-11-09 멀티­채널 ｉ²ｓ 송신 제어 시스템 및 방법

Country Status (7)

Country Link
US (1) US9842071B2 (https=)
EP (1) EP3218813B1 (https=)
JP (1) JP2018502406A (https=)
KR (1) KR20170084043A (https=)
CN (1) CN107111587A (https=)
TW (1) TW201633164A (https=)
WO (1) WO2016077189A1 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210141755A (ko) * 2019-05-13 2021-11-23 예놉틱 옵틱컬 시스템즈 게엠베하 신호 내의 플랭크의 시간을 결정하기 위한 방법 및 평가 유닛

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GB2539445A (en) * 2015-06-16 2016-12-21 Nordic Semiconductor Asa Data processing
US10007485B2 (en) * 2016-01-12 2018-06-26 Oracle International Corporation Zero-delay compression FIFO buffer
CN106911987B (zh) * 2017-02-21 2019-11-05 珠海全志科技股份有限公司 主控端、设备端、传输多声道音频数据的方法和系统
CN108628793B (zh) * 2017-03-20 2021-04-02 华大半导体有限公司 Spi通信电路及方法
FR3066033B1 (fr) * 2017-05-05 2019-06-21 Stmicroelectronics (Rousset) Sas Dispositif d'etage tampon, en particulier apte a etre connecte sur un bus du type interface de peripherique serie
CN108304282B (zh) * 2018-03-07 2021-04-20 郑州云海信息技术有限公司 一种双bios的控制方法及相关装置
TWI699656B (zh) * 2018-12-27 2020-07-21 新唐科技股份有限公司 可切換的i2s介面
DE112020004915T5 (de) * 2019-10-10 2022-06-30 Microchip Technology Incorporated Serielle n-kanal-peripheriekommunikation und darauf bezogene systeme, verfahren und vorrichtungen
IT202000006322A1 (it) 2020-03-25 2021-09-25 Stmicroelectronics Application Gmbh Sistema di elaborazione comprendente un’interfaccia periferica seriale con code, relativo circuito integrato, dispositivo e procedimento
RU2762040C1 (ru) * 2020-11-06 2021-12-15 СВИ Коммуникатионс-унд Компутер ГмбХ Система объединения цифровых потоков и способ объединения цифровых потоков (варианты)

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US5517627A (en) * 1992-09-18 1996-05-14 3Com Corporation Read and write data aligner and method
JP2004240713A (ja) * 2003-02-06 2004-08-26 Matsushita Electric Ind Co Ltd データ転送方法及びデータ転送装置
EP1447739A1 (en) * 2003-02-12 2004-08-18 Deutsche Thomson-Brandt Gmbh Method and apparatus for preprocessing input/output signals of/to different types of interfaces using a common format
JP4354268B2 (ja) * 2003-12-22 2009-10-28 株式会社河合楽器製作所 信号処理装置
KR100881191B1 (ko) 2007-03-27 2009-02-05 삼성전자주식회사 멀티 프로토콜 씨리얼 인터페이스 장치 및 그에 따른ｓｏｃ 장치
EP2294858A4 (en) * 2008-06-23 2014-07-02 Hart Comm Foundation ANALYZER FOR A WIRELESS COMMUNICATION NETWORK
US8255593B2 (en) * 2009-09-29 2012-08-28 Oracle America, Inc. Direct memory access with striding across memory
US20110242355A1 (en) * 2010-04-05 2011-10-06 Qualcomm Incorporated Combining data from multiple image sensors
CN102117478B (zh) * 2011-02-09 2012-10-03 河南科技大学 批量图像数据的实时处理方法及系统

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20210141755A (ko) * 2019-05-13 2021-11-23 예놉틱 옵틱컬 시스템즈 게엠베하 신호 내의 플랭크의 시간을 결정하기 위한 방법 및 평가 유닛

Also Published As

Publication number Publication date
EP3218813A1 (en) 2017-09-20
EP3218813B1 (en) 2022-05-04
US9842071B2 (en) 2017-12-12
CN107111587A (zh) 2017-08-29
WO2016077189A1 (en) 2016-05-19
TW201633164A (zh) 2016-09-16
US20160132440A1 (en) 2016-05-12
JP2018502406A (ja) 2018-01-25

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Date Code Title Description
PA0105 International application

Patent event date: 20170426

Patent event code: PA01051R01D

Comment text: International Patent Application

PG1501 Laying open of application
PC1203 Withdrawal of no request for examination