JP2018160626A - 半導体装置 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 239000012535 impurity Substances 0.000 claims description 24
- 230000015556 catabolic process Effects 0.000 claims description 17
- 239000000758 substrate Substances 0.000 description 26
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- 230000002457 bidirectional effect Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
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- 239000013078 crystal Substances 0.000 description 1
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- 238000009792 diffusion process Methods 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
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Abstract
【解決手段】半導体装置は、カソードが第1端子に接続された第1ダイオードと、カソードが第2端子に接続された第2ダイオードと、アノードが前記第1端子に接続された第3ダイオードと、アノードが前記第2端子に接続された第4ダイオードと、アノードが前記第1ダイオードのアノード及び前記第2ダイオードのアノードに接続され、カソードが前記第3ダイオードのカソード及び前記第4ダイオードのカソードに接続された第5ダイオードと、を備える。前記第5ダイオードの耐圧は、前記第1ダイオードの耐圧、前記第2ダイオードの耐圧、前記第3ダイオードの耐圧及び前記第4ダイオードの耐圧よりも低い。
【選択図】図4
Description
先ず、第1の実施形態について説明する。
図1は、本実施形態に係る半導体装置の使用例を示す回路図である。
図2は、本実施形態に係る半導体装置を示す平面図である。
図3は、図2に示すA−A’線による断面図である。
図4は、本実施形態に係る半導体装置を示す回路図である。
図2及び図3に示すように、p−形エピタキシャル層11aとn+形コンタクト層14aとの界面には、p−形エピタキシャル層11aをアノードとし、n+形コンタクト層14aをカソードとするダイオードD1が形成される。p−形エピタキシャル層11bとn+形コンタクト層14bとの界面には、p−形エピタキシャル層11bをアノードとし、n+形コンタクト層14bをカソードとするダイオードD2が形成される。
本実施形態に係る半導体装置1においては、1つのチップ内に双方向の電流経路Ia及びIbを実現することができる。これにより、双方向の保護回路を低コスト且つ省スペースで実現することができる。また、容量が大きなダイオードD5を、他のダイオードと直列に接続することにより、半導体装置1全体の容量を小さくすることができる。
次に、第1の実施形態の変形例について説明する。
図5は、本変形例に係る半導体装置を示す平面図である。
なお、第1の実施形態と比較して、ダイオードD5の容量は増加するが、上述のクローバー回路の構造により、電極18aと電極18bとの間の容量はほとんど増加しない。
次に、第2の実施形態について説明する。
図6は、本実施形態に係る半導体装置を示す平面図である。
図7は、図6に示すB−B’線による断面図である。
図8は、本実施形態に係る半導体装置を示す回路図である。
本実施形態に係る半導体装置2も、前述の第1の実施形態に係る半導体装置1(図1〜図4参照)と同様に、例えば保護回路として使用される。
本実施形態に係る半導体装置2においては、1つのチップ内に双方向の電流経路Ic及びIdを実現することができる。これにより、双方向の保護回路を低コスト且つ省スペースで実現することができる。
次に、第2の実施形態の変形例について説明する。
図9は、本変形例に係る半導体装置を示す断面図である。
Claims (9)
- カソードが第1端子に接続された第1ダイオードと、
カソードが第2端子に接続された第2ダイオードと、
アノードが前記第1端子に接続された第3ダイオードと、
アノードが前記第2端子に接続された第4ダイオードと、
アノードが前記第1ダイオードのアノード及び前記第2ダイオードのアノードに接続され、カソードが前記第3ダイオードのカソード及び前記第4ダイオードのカソードに接続された第5ダイオードと、
を備え、
前記第5ダイオードの耐圧が、前記第1ダイオードの耐圧、前記第2ダイオードの耐圧、前記第3ダイオードの耐圧及び前記第4ダイオードの耐圧よりも低い半導体装置。 - 前記第5ダイオードは、第1導電形の第1ウェルと第2導電形の第2ウェルとの界面に形成され、
前記第1ダイオードは、前記第1ウェルに接続され、前記第1導電形であり、不純物濃度が前記第1ウェルの不純物濃度よりも低い第1層と、前記第1端子に接続され、第2導電形である第2層との界面に形成され、
前記第2ダイオードは、前記第1ウェルに接続され、前記第1導電形であり、不純物濃度が前記第1ウェルの不純物濃度よりも低い第3層と、前記第2端子に接続され、第2導電形である第4層との界面に形成され、
前記第3ダイオードは、前記第1端子に接続され、前記第1導電形であり、不純物濃度が前記第1ウェルの不純物濃度よりも低い第5層と、前記第2ウェルとの界面に形成され、
前記第4ダイオードは、前記第2端子に接続され、前記第1導電形であり、不純物濃度が前記第1ウェルの不純物濃度よりも低い第6層と、前記第2ウェルとの界面に形成された請求項1記載の半導体装置。 - 第1電極と、
第2電極と、
第1導電形の第1ウェルと、
前記第1ウェルに接し、第2導電形の第2ウェルと、
前記第1ウェルに接続され、前記第1導電形であり、不純物濃度が前記第1ウェルの不純物濃度よりも低い第1層と、
前記第1電極に接続され、前記第1層に接し、前記第2導電形である第2層と、
前記第1ウェルに接続され、前記第1導電形であり、不純物濃度が前記第1ウェルの不純物濃度よりも低い第3層と、
前記第2電極に接続され、前記第3層に接し、前記第2導電形である第4層と、
前記第1電極に接続され、前記第2ウェルに接し、前記第1導電形であり、不純物濃度が前記第1ウェルの不純物濃度よりも低い第5層と、
前記第2電極に接続され、前記第2ウェルに接し、前記第1導電形であり、不純物濃度が前記第1ウェルの不純物濃度よりも低い第6層と、
を備えた半導体装置。 - 前記第1ウェルと前記第2ウェルとの界面は櫛状である請求項2または3に記載の半導体装置。
- 真性半導体層をさらに備え、
前記第1ウェル、前記第2ウェル、前記第1層、前記第3層、前記第5層及び前記第6層は、前記真性半導体層上に配置され、前記真性半導体層に接した請求項2〜4のいずれか1つに記載の半導体装置。 - カソードが第1端子に接続された第1ダイオードと、
カソードが第2端子に接続された第2ダイオードと、
カソードが前記第1端子に接続され、アノードが前記第2ダイオードのアノードに接続され、耐量が前記第2ダイオードの耐量よりも低い第3ダイオードと、
カソードが前記第2端子に接続され、アノードが前記第1ダイオードのアノードに接続され、耐量が前記第1ダイオードの耐量よりも低い第4ダイオードと、
を備えた半導体装置。 - 前記第1ダイオードは、前記第1端子に接続され、第1導電形の第1層と、第2導電形の第2層との界面に形成され、
前記第2ダイオードは、前記第2導電形の第3層と、前記第2端子に接続され、前記第1導電形の第4層との界面に形成され、
前記第3ダイオードは、前記第1層と、前記第3層に接続され、第2導電形であり、不純物濃度が前記第3層の不純物濃度よりも高い第5層との界面に形成され、
前記第4ダイオードは、前記第2層に接続され、前記第2導電形であり、不純物濃度が前記第2層の不純物濃度よりも高い第6層と、前記第2端子に接続され、前記第1導電形の第7層との界面に形成され、
前記第2層と前記第3層とは、電気的に分離された請求項6記載の半導体装置。 - 前記第2層と前記第3層との間に設けられ、第1導電形である第8層をさらに備えた請求項7記載の半導体装置。
- 前記第2層と前記第3層との間に設けられた絶縁部材をさらに備えた請求項7記載の半導体装置。
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JPH05226645A (ja) * | 1991-06-11 | 1993-09-03 | Sgs Thomson Microelectron Sa | 双方向過電圧保護装置 |
JPH10294475A (ja) * | 1997-04-17 | 1998-11-04 | Toshiba Corp | 半導体装置とその製造方法 |
JP2000299477A (ja) * | 1999-04-12 | 2000-10-24 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US20100155774A1 (en) * | 2008-12-23 | 2010-06-24 | Amazing Microelectronic Corp. | Bi-directional transient voltage suppression device and forming method thereof |
JP2014167870A (ja) * | 2013-02-28 | 2014-09-11 | Murata Mfg Co Ltd | Esd保護デバイス |
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JP2016171233A (ja) * | 2015-03-13 | 2016-09-23 | 株式会社東芝 | 半導体装置 |
US20160300939A1 (en) * | 2015-04-10 | 2016-10-13 | Silergy Semiconductor Technology (Hangzhou) Ltd | Bi-directional punch-through semiconductor device and manufacturing method thereof |
Cited By (1)
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US11784220B2 (en) | 2020-12-25 | 2023-10-10 | Kabushiki Kaisha Toshiba | Semiconductor device |
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