JP2018159872A - 半導体光素子及びその製造方法 - Google Patents
半導体光素子及びその製造方法 Download PDFInfo
- Publication number
- JP2018159872A JP2018159872A JP2017058070A JP2017058070A JP2018159872A JP 2018159872 A JP2018159872 A JP 2018159872A JP 2017058070 A JP2017058070 A JP 2017058070A JP 2017058070 A JP2017058070 A JP 2017058070A JP 2018159872 A JP2018159872 A JP 2018159872A
- Authority
- JP
- Japan
- Prior art keywords
- resin layer
- bonding pad
- layer
- inorganic film
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003287 optical effect Effects 0.000 title claims abstract description 93
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000011347 resin Substances 0.000 claims abstract description 169
- 229920005989 resin Polymers 0.000 claims abstract description 169
- 239000000758 substrate Substances 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims description 8
- 230000002093 peripheral effect Effects 0.000 claims description 7
- 229920001187 thermosetting polymer Polymers 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 244
- 230000001681 protective effect Effects 0.000 description 20
- 238000005253 cladding Methods 0.000 description 17
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 11
- 239000002184 metal Substances 0.000 description 9
- 239000012071 phase Substances 0.000 description 9
- 230000000052 comparative effect Effects 0.000 description 8
- 239000012792 core layer Substances 0.000 description 7
- 238000001312 dry etching Methods 0.000 description 6
- 238000007747 plating Methods 0.000 description 6
- 230000001902 propagating effect Effects 0.000 description 6
- 239000002243 precursor Substances 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 4
- 230000008602 contraction Effects 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000004528 spin coating Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000006748 scratching Methods 0.000 description 2
- 230000002393 scratching effect Effects 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/21—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour by interference
- G02F1/225—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure
- G02F1/2257—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour by interference in an optical waveguide structure the optical waveguides being made of semiconducting material
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/015—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction
- G02F1/025—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on semiconductor elements having potential barriers, e.g. having a PN or PIN junction in an optical waveguide structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
- H01S5/0265—Intensity modulators
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/10—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region
- H01S5/12—Construction or shape of the optical resonator, e.g. extended or external cavity, coupled cavities, bent-guide, varying width, thickness or composition of the active region the resonator having a periodic structure, e.g. in distributed feedback [DFB] lasers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
- H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
- H01S5/227—Buried mesa structure ; Striped active layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/03444—Manufacturing methods by blanket deposition of the material of the bonding area in gaseous form
- H01L2224/0345—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/03—Manufacturing methods
- H01L2224/034—Manufacturing methods by blanket deposition of the material of the bonding area
- H01L2224/0346—Plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/0502—Disposition
- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
- H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05144—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05166—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05099—Material
- H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05184—Tungsten [W] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05556—Shape in side view
- H01L2224/05558—Shape in side view conformal layer on a patterned surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05567—Disposition the external layer being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05571—Disposition the external layer being disposed in a recess of the surface
- H01L2224/05572—Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Optics & Photonics (AREA)
- Nonlinear Science (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Electromagnetism (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Plasma & Fusion (AREA)
- Optical Modulation, Optical Deflection, Nonlinear Optics, Optical Demodulation, Optical Logic Elements (AREA)
- Wire Bonding (AREA)
Abstract
【解決手段】 基板上に設けられたメサ状の光導波路と、前記光導波路上に設けられた変調用電極と、前記光導波路の側面を埋め込む第1樹脂層と、前記第1樹脂層上に設けられたボンディングパッドと、前記変調用電極と前記ボンディングパッドとを接続する接続配線と、を備え、前記ボンディングパッドは、前記第1樹脂層上に設けられた第2樹脂層に側面の一部を覆われ、前記接続配線は、前記第2樹脂層上を延在する、半導体光素子。
【選択図】 図4
Description
最初に、本願発明の実施形態の内容を列記して説明する。
本願発明は、(1)基板上に設けられたメサ状の光導波路と、前記光導波路上に設けられた変調用電極と、前記光導波路の側面を埋め込む第1樹脂層と、前記第1樹脂層上に設けられたボンディングパッドと、前記変調用電極と前記ボンディングパッドとを接続する接続配線と、を備え、前記ボンディングパッドは、前記第1樹脂層上に設けられた第2樹脂層に側面の一部を覆われ、前記接続配線は、前記第2樹脂層上を延在する、半導体光素子である。
(2)前記ボンディングパッドは、下部領域の上面に上部領域が積層された構造を有し、前記下部領域と前記上部領域との積層面において前記上部領域の幅が前記下部領域の幅よりも小さく、前記下部領域の上面において前記上部領域が設けられていない領域は、前記第2樹脂層によって覆われていてもよい。
(3)前記上部領域の厚みは、前記第2樹脂層の厚みよりも大きくてもよい。
(4)前記第1樹脂層と前記ボンディングパッドとの間に第1無機膜を備えていてもよい。
(5)前記第2樹脂層上に設けられた第2無機膜と、前記第2無機膜上に設けられた第3無機膜と、を備え、前記ボンディングパッドは、前記第2樹脂層上まで延在し、前記第2無機膜および前記第3無機膜は、前記第2樹脂層上まで延在した前記ボンディングパッドの部分の周縁部分の上下を挟んでいてもよい。
(6)前記第1樹脂層は、前記第2樹脂層よりも固くてもよい。
(7)前記ボンディングパッドから最近接の側面と、前記ボンディングパッドとの間において、前記基板上に、前記メサ状の光導波路と同じ半導体積層構造が設けられていてもよい。
本願他の発明は、(8)基板上に設けられたメサ状の光導波路の側面を第1樹脂層で埋め込む工程と、前記光導波路上に変調用電極を形成する工程と、前記第1樹脂層上にボンディングパッドを形成する工程と、前記第1樹脂層上に第2樹脂層を形成する工程と、前記変調用電極と前記ボンディングパッドとを接続し、前記第2樹脂層上を延在する接続配線を形成する工程と、を含み、前記第2樹脂層を形成する際に、前記ボンディングパッドの側面の一部が前記第2樹脂層に覆われるようにする、半導体光素子の製造方法である。
(9)前記第1樹脂層で埋め込む工程において、前記第1樹脂層に熱硬化処理を行い、前記第2樹脂層を形成する工程において、前記第2樹脂層に熱硬化処理を行ってもよい。
本願発明の実施形態に係る半導体光素子及び半導体光素子の製造方法の具体例を、以下に図面を参照しつつ説明する。なお、本願発明はこれらの例示に限定されるものではなく、特許請求の範囲によって示され、特許請求の範囲と均等の意味及び範囲内での全ての変更が含まれることが意図される。また、本願発明の効果がある限りにおいて他の成分が含まれていてもよい。
図1は、第1実施形態に係る半導体光素子である光変調器100の光導波路部分の平面図である。図1のように、第1実施形態に係る光変調器100は、基板1上に、入力導波路31a、出力導波路31b、光カプラ32a,32b、及び複数のマッハツェンダ変調器30が設けられている。入力導波路31a、出力導波路31b、及び光カプラ32a,32bは、メサ状の光導波路からなる。光カプラ32a,32bは、MMI(Multimode Interferometer)型の光カプラである。複数のマッハツェンダ変調器30は、メサ状の光導波路の経路を組み合わせた構成をしている。入力導波路31aから入力された光は、光カプラ32aで分岐され、マッハツェンダ変調器30を経由した後、光カプラ32bで合波されて、出力導波路31bに出力される。光変調器100の大きさは、例えば10mm×4mmである。
図14は、第2実施形態について説明するための図である。図14は、図2のB−B線断面に相当する。本実施形態においては、スクライブラインSLの領域に、アーム導波路34a,34bのメサ状の導波路と同じ半導体構造が設けられている。すなわち、スクライブラインSLにおいて、基板1上に、下部クラッド層2、コア層3、上部クラッド層4及びコンタクト層5が積層されている。このコンタクト層5の上面が露出している。
実施例1では、図15(a)に示すように、図4で説明したボンディングパッドを作成した。基板1には、厚さ600μmの反絶縁性のInPを用いた。保護膜14には、厚さ200nmのSiONまたはSiO2を用いた。第1樹脂層15には、厚さ4μmのBCBを用いた。第1無機膜16には、厚さ200nmのSiONを用いた。第1下地層7には、厚さ50nmのTiWを用いた。第1Au層8には、厚さ4μmのAuを用いた。第2下地層9には、厚さ50nmのTiWを用いた。第2Au層10には、厚さ4μmのAuを用いた。第2樹脂層17には、厚さ2.5μmのBCBを用いた。第2無機膜18には、厚さ300nmのSiO2を用いた。第3無機膜19には、厚さ500nmのSiON/SiNを用いた。
図15(b)に示すように、比較例1では、第1樹脂層15上に、第2下地層9を形成し、第2下地層9上に第2Au層10を形成した。厚さについては、実施例1と同様である。
図15(c)に示すように、比較例2では、基板1上に保護膜14を形成し、保護膜14上に第2下地層9を形成し、第2下地層9上に第2Au層10を形成した。厚さについては、実施例1と同様である。
Claims (9)
- 基板上に設けられたメサ状の光導波路と、
前記光導波路上に設けられた変調用電極と、
前記光導波路の側面を埋め込む第1樹脂層と、
前記第1樹脂層上に設けられたボンディングパッドと、
前記変調用電極と前記ボンディングパッドとを接続する接続配線と、を備え、
前記ボンディングパッドは、前記第1樹脂層上に設けられた第2樹脂層に側面の一部を覆われ、
前記接続配線は、前記第2樹脂層上を延在する、半導体光素子。 - 前記ボンディングパッドは、下部領域の上面に上部領域が積層された構造を有し、
前記下部領域と前記上部領域との積層面において前記上部領域の幅が前記下部領域の幅よりも小さく、
前記下部領域の上面において前記上部領域が設けられていない領域は、前記第2樹脂層によって覆われている、請求項1記載の半導体光素子。 - 前記上部領域の厚みは、前記第2樹脂層の厚みよりも大きい、請求項1または2に記載の半導体光素子。
- 前記第1樹脂層と前記ボンディングパッドとの間に第1無機膜を備える、請求項1〜3のいずれか一項に記載の半導体光素子。
- 前記第2樹脂層上に設けられた第2無機膜と、
前記第2無機膜上に設けられた第3無機膜と、を備え、
前記ボンディングパッドは、前記第2樹脂層上まで延在し、
前記第2無機膜および前記第3無機膜は、前記第2樹脂層上まで延在した前記ボンディングパッドの部分の周縁部分の上下を挟む、請求項1〜4のいずれか一項に記載の半導体光素子。 - 前記第1樹脂層は、前記第2樹脂層よりも固い、請求項1〜5のいずれか一項に記載の半導体光素子。
- 前記ボンディングパッドから最近接の側面と、前記ボンディングパッドとの間において、前記基板上に、前記メサ状の光導波路と同じ半導体積層構造が設けられている、請求項1〜6のいずれか一項に記載の半導体光素子。
- 基板上に設けられたメサ状の光導波路の側面を第1樹脂層で埋め込む工程と、
前記光導波路上に変調用電極を形成する工程と、
前記第1樹脂層上にボンディングパッドを形成する工程と、
前記第1樹脂層上に第2樹脂層を形成する工程と、
前記変調用電極と前記ボンディングパッドとを接続し、前記第2樹脂層上を延在する接続配線を形成する工程と、を含み、
前記第2樹脂層を形成する際に、前記ボンディングパッドの側面の一部が前記第2樹脂層に覆われるようにする、半導体光素子の製造方法。 - 前記第1樹脂層で埋め込む工程において、前記第1樹脂層に熱硬化処理を行い、
前記第2樹脂層を形成する工程において、前記第2樹脂層に熱硬化処理を行う、請求項8記載の半導体光素子の製造方法。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017058070A JP6862983B2 (ja) | 2017-03-23 | 2017-03-23 | 半導体光素子及びその製造方法 |
US15/914,826 US10248000B2 (en) | 2017-03-23 | 2018-03-07 | Semiconductor optical element and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017058070A JP6862983B2 (ja) | 2017-03-23 | 2017-03-23 | 半導体光素子及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2018159872A true JP2018159872A (ja) | 2018-10-11 |
JP6862983B2 JP6862983B2 (ja) | 2021-04-21 |
Family
ID=63582426
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2017058070A Active JP6862983B2 (ja) | 2017-03-23 | 2017-03-23 | 半導体光素子及びその製造方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US10248000B2 (ja) |
JP (1) | JP6862983B2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020052361A (ja) * | 2018-09-28 | 2020-04-02 | 住友電気工業株式会社 | 半導体装置およびその製造方法 |
JP2021162641A (ja) * | 2020-03-31 | 2021-10-11 | 住友大阪セメント株式会社 | 光制御素子とそれを用いた光変調デバイス並びに光送信装置 |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11175520B2 (en) * | 2018-02-09 | 2021-11-16 | Mitsubishi Electric Corporation | Optical semiconductor device and method for manufacturing the same |
JP7077824B2 (ja) * | 2018-07-06 | 2022-05-31 | 住友電気工業株式会社 | マッハツェンダー変調器を作製する方法 |
Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54110784A (en) * | 1978-02-17 | 1979-08-30 | Nec Corp | Semiconductor device |
JPS5728344A (en) * | 1980-07-29 | 1982-02-16 | Nec Corp | Semiconductor device |
JPS62214625A (ja) * | 1986-03-17 | 1987-09-21 | Hitachi Micro Comput Eng Ltd | 半導体装置 |
JPS63293930A (ja) * | 1987-05-27 | 1988-11-30 | Hitachi Ltd | 半導体装置における電極 |
JPH11340319A (ja) * | 1998-05-26 | 1999-12-10 | Nec Corp | 多層配線構造及びそれを有する半導体装置並びにそれらの製造方法 |
US20030223672A1 (en) * | 2002-03-08 | 2003-12-04 | Joyner Charles H. | Insertion loss reduction, passivation and/or planarization and in-wafer testing of integrated optical components in photonic integrated circuits (PICs) |
JP2004126108A (ja) * | 2002-10-01 | 2004-04-22 | Toshiba Corp | 半導体光変調器及び光変調システム |
JP2006339247A (ja) * | 2005-05-31 | 2006-12-14 | Seiko Epson Corp | 光素子 |
WO2008044537A1 (en) * | 2006-10-05 | 2008-04-17 | Nec Corporation | Semiconductor package and method for producing semiconductor package |
JP2010008869A (ja) * | 2008-06-30 | 2010-01-14 | Fujitsu Ltd | マッハツェンダ型光変調器 |
JP2012123184A (ja) * | 2010-12-08 | 2012-06-28 | Sumitomo Electric Ind Ltd | 半導体光変調素子及びその製造方法 |
JP2013055272A (ja) * | 2011-09-06 | 2013-03-21 | Panasonic Corp | 半導体装置 |
JP2014219442A (ja) * | 2013-05-01 | 2014-11-20 | 住友電気工業株式会社 | 半導体光素子の製造方法 |
JP2016029469A (ja) * | 2014-07-14 | 2016-03-03 | 住友電気工業株式会社 | 半導体光変調器および半導体光変調器の製造方法 |
JP2016031377A (ja) * | 2014-07-25 | 2016-03-07 | 住友電気工業株式会社 | 光半導体素子およびその製造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002232004A (ja) | 2001-01-31 | 2002-08-16 | Kyocera Corp | Ledアレイ |
JP5678528B2 (ja) | 2010-09-07 | 2015-03-04 | 住友電気工業株式会社 | 半導体光デバイスの製造方法 |
JP5767864B2 (ja) | 2011-06-07 | 2015-08-26 | 日本オクラロ株式会社 | 光素子、光素子を含む変調器モジュール、光素子を含むレーザ集積変調器モジュール、及び、光素子の製造方法 |
JP5795970B2 (ja) | 2012-03-01 | 2015-10-14 | Nttエレクトロニクス株式会社 | ボンディングパッド電極形成方法 |
JP6236947B2 (ja) | 2013-07-16 | 2017-11-29 | 住友電気工業株式会社 | 半導体光素子を製造する方法、および半導体光素子 |
-
2017
- 2017-03-23 JP JP2017058070A patent/JP6862983B2/ja active Active
-
2018
- 2018-03-07 US US15/914,826 patent/US10248000B2/en active Active
Patent Citations (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS54110784A (en) * | 1978-02-17 | 1979-08-30 | Nec Corp | Semiconductor device |
JPS5728344A (en) * | 1980-07-29 | 1982-02-16 | Nec Corp | Semiconductor device |
JPS62214625A (ja) * | 1986-03-17 | 1987-09-21 | Hitachi Micro Comput Eng Ltd | 半導体装置 |
JPS63293930A (ja) * | 1987-05-27 | 1988-11-30 | Hitachi Ltd | 半導体装置における電極 |
JPH11340319A (ja) * | 1998-05-26 | 1999-12-10 | Nec Corp | 多層配線構造及びそれを有する半導体装置並びにそれらの製造方法 |
US20030223672A1 (en) * | 2002-03-08 | 2003-12-04 | Joyner Charles H. | Insertion loss reduction, passivation and/or planarization and in-wafer testing of integrated optical components in photonic integrated circuits (PICs) |
JP2004126108A (ja) * | 2002-10-01 | 2004-04-22 | Toshiba Corp | 半導体光変調器及び光変調システム |
JP2006339247A (ja) * | 2005-05-31 | 2006-12-14 | Seiko Epson Corp | 光素子 |
WO2008044537A1 (en) * | 2006-10-05 | 2008-04-17 | Nec Corporation | Semiconductor package and method for producing semiconductor package |
JP2010008869A (ja) * | 2008-06-30 | 2010-01-14 | Fujitsu Ltd | マッハツェンダ型光変調器 |
JP2012123184A (ja) * | 2010-12-08 | 2012-06-28 | Sumitomo Electric Ind Ltd | 半導体光変調素子及びその製造方法 |
JP2013055272A (ja) * | 2011-09-06 | 2013-03-21 | Panasonic Corp | 半導体装置 |
JP2014219442A (ja) * | 2013-05-01 | 2014-11-20 | 住友電気工業株式会社 | 半導体光素子の製造方法 |
JP2016029469A (ja) * | 2014-07-14 | 2016-03-03 | 住友電気工業株式会社 | 半導体光変調器および半導体光変調器の製造方法 |
JP2016031377A (ja) * | 2014-07-25 | 2016-03-07 | 住友電気工業株式会社 | 光半導体素子およびその製造方法 |
Non-Patent Citations (1)
Title |
---|
YAGI, HIDEYUKI ET AL.: "26 Gbit/s Direct Modulation of AlGaInAs/InP Lasers with Ridge-Waveguide Structure Buried by Benzocyc", 2009 IEEE INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE & RELATED MATERIALS, vol. ThB1.3, JPN6020033826, 10 May 2009 (2009-05-10), US, pages 371 - 374, XP031467180, ISSN: 0004342009 * |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020052361A (ja) * | 2018-09-28 | 2020-04-02 | 住友電気工業株式会社 | 半導体装置およびその製造方法 |
JP7110879B2 (ja) | 2018-09-28 | 2022-08-02 | 住友電気工業株式会社 | 半導体装置およびその製造方法 |
JP2021162641A (ja) * | 2020-03-31 | 2021-10-11 | 住友大阪セメント株式会社 | 光制御素子とそれを用いた光変調デバイス並びに光送信装置 |
JP7054068B2 (ja) | 2020-03-31 | 2022-04-13 | 住友大阪セメント株式会社 | 光制御素子とそれを用いた光変調デバイス並びに光送信装置 |
Also Published As
Publication number | Publication date |
---|---|
US20180275482A1 (en) | 2018-09-27 |
JP6862983B2 (ja) | 2021-04-21 |
US10248000B2 (en) | 2019-04-02 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6862983B2 (ja) | 半導体光素子及びその製造方法 | |
US7939352B2 (en) | Selective area metal bonding Si-based laser | |
US9280030B2 (en) | Method for producing semiconductor optical device and semiconductor optical device | |
US20210066537A1 (en) | Method of manufacturing a iii-v based optoelectronic device | |
JP2016042575A (ja) | 光集積回路を製造する方法 | |
US8618638B2 (en) | Semiconductor optical modulator and method for manufacturing the same | |
US11079539B2 (en) | Semiconductor device and manufacturing method of the same | |
US9638980B2 (en) | Modulator and production method thereof | |
WO2021094473A1 (en) | Optoelectronic device and method of manufacture thereof | |
JP6205826B2 (ja) | 半導体光素子の製造方法 | |
JP4915945B2 (ja) | 光デバイスの製造方法 | |
JP6828519B2 (ja) | 半導体素子の製造方法 | |
JP5257281B2 (ja) | 半導体装置及びその製造方法 | |
US9885936B2 (en) | Mach-Zehnder modulator, method for fabricating Mach-Zehnder modulator | |
JP2013016648A (ja) | 半導体光集積素子の製造方法 | |
JP7110879B2 (ja) | 半導体装置およびその製造方法 | |
CN111684344B (zh) | 光半导体元件及其制造方法 | |
EP4058841A1 (en) | Optoelectronic device and method of manufacture thereof | |
EP4062212A1 (en) | Hetergenous integration and electro-optic modulation of iii-nitride photonics on a silicon photonic platform | |
US10403786B2 (en) | Optoelectronic system and method for its fabrication | |
JP2013044794A (ja) | 光半導体素子の製造方法 | |
JP5760667B2 (ja) | 光半導体デバイスの製造方法 | |
JP3798379B2 (ja) | 光モジュール、及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20190924 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20200826 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20200908 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20201105 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20210302 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20210315 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6862983 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |