JP2018137439A - ナノワイヤサイズの光電構造及びその選択された部分を改質する方法 - Google Patents
ナノワイヤサイズの光電構造及びその選択された部分を改質する方法 Download PDFInfo
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Abstract
【解決手段】LED構造は、支持体と、支持体上に配置された複数のナノワイヤ100とを含み、各ナノワイヤは先端部115及び側壁113を含む。LED構造を製造する方法は、ナノワイヤの形成中又は形成後にナノワイヤの側壁の導電率と比較してナノワイヤの先端部の導電率を低下させるか又は零にすることを含む。
【選択図】図5
Description
Claims (43)
- 支持体と、前記支持体の上に配置された複数のナノワイヤとを備え、各ナノワイヤが先端部及び側壁を備えるLED構造を製造する方法であって、
前記ナノワイヤの形成中又は形成後に前記ナノワイヤの前記側壁の導電率と比較して前記ナノワイヤの前記先端部の導電率を低下させるか又は零にすることを含むことを特徴とする方法。 - ナノワイヤ成長条件を制御しない場合の前記先端部の導電率と比較して前記先端部の導電率が少なくとも1桁小さくなるようにナノワイヤ成長条件を制御することを更に含むことを特徴とする請求項1に記載の方法。
- 前記先端部の導電率を低下させるか又は零にすることは、前記ナノワイヤの形成後に前記ナノワイヤを覆う絶縁層を形成することを含むことを特徴とする請求項1に記載の方法。
- 前記絶縁層は、前記先端部及び前記側壁の上に前記絶縁層が積層されるようにナノワイヤのアレイを覆うように形成され、その後、前記側壁の上の前記絶縁層の全体又は一部が除去されるが、前記先端部の上の、少なくとも、より厚い部分の前記絶縁層が残る条件の下で、前記アレイがエッチングされることを特徴とする請求項3に記載の方法。
- 前記絶縁層はSiOxを含むことを特徴とする請求項4に記載の方法。
- 前記SiOxはSiO2であることを特徴とする請求項5に記載の方法。
- 形成される前記絶縁層は、前記側壁の上よりも前記先端部の上の方が厚いことを特徴とする請求項4から6のいずれか1項に記載の方法。
- 前記エッチングは異方性エッチングであることを特徴とする請求項7に記載の方法。
- 前記ナノワイヤは、第1の導電型の半導体コアと第2の導電型の半導体シェルとを備え、且つ前記側壁及び前記先端部は前記第2の導電型の半導体シェルを構成することを特徴とする請求項1に記載の方法。
- 前記シェルは連続層として形成されることを特徴とする請求項9に記載の方法。
- 前記シェルは、低導電率材料及び高導電率材料を含む連続層として形成され、前記高導電率材料は、前記先端部よりも前記側壁に優先的に形成されることを特徴とする請求項10に記載の方法。
- 前記低導電率材料はp−AlGaNより成り且つ前記高導電率材料はp−GaNを含むことを特徴とする請求項11に記載の方法。
- 前記シェルは、前記側壁に複数の低導電率層及び複数の高導電率層を設けるように形成されることを特徴とする請求項11又は12に記載の方法。
- 前記シェルは、前記先端部に単一の複合低導電率層を設けるように形成されることを特徴とする請求項13に記載の方法。
- 前記シェルは、前記先端部に複数の低導電率層及び複数の高導電率層を設けるように形成され、前記先端部の前記高導電率層の厚さが前記側壁の前記高導電率層の厚さより薄いために前記先端部の導電率が前記側壁の導電率より低いことを特徴とする請求項13記載の方法。
- 前記先端部は非導電性であることを特徴とする請求項15に記載の方法。
- 前記ナノワイヤの前記先端部に高抵抗材料を形成するが、前記ナノワイヤの前記側壁には形成しないことを更に含むことを特徴とする請求項10に記載の方法。
- 前記高抵抗材料は、前記シェルの完成後に前記先端部に選択的に形成されることを特徴とする請求項17に記載の方法。
- 前記高抵抗材料は、前記シェルの完成前に前記先端部に選択的に形成されることを特徴とする請求項17に記載の方法。
- 前記高抵抗材料は、2〜5%のMgを含むpGaNより成り且つ10〜50のV/III比を使用してMOCVDにより成長されることを特徴とする請求項19に記載の方法。
- 前記ナノワイヤ構造は多層構造を含み、前記ナノワイヤの少なくとも1つの層はH2を含むキャリアガスを使用して形成されることを特徴とする請求項1に記載の方法。
- 前記H2は少なくとも50sccmのH2を含むことを特徴とする請求項21に記載の方法。
- 動作中に光を発生する活性領域を提供するpn接合又はpin接合を形成するために、前記第1の導電型の半導体ナノワイヤコアは前記第2の導電型の半導体シェルにより取り囲まれることを特徴とする請求項10に記載の方法。
- 前記第1の導電型はn型であり、前記第2の導電型はp型であることを特徴とする請求項23に記載の方法。
- 前記ナノワイヤコアは、前記ナノワイヤアレイの製造中にn型バッファ層を含む支持体から成長することを特徴とする請求項10に記載の方法。
- 前記支持体は誘電体マスク層を更に備え、コアは前記バッファ層から前記マスク層の開口部を通して突出し、前記シェルは前記マスク層の上に配置されることを特徴とする請求項25に記載の方法。
- 前記支持体は、前記バッファ層の下に基板層を更に備えることを特徴とする請求項25に記載の方法。
- 前記基板層はAl2O3を含むことを特徴とする請求項27に記載の方法。
- 前記支持体層は反射層を更に備えることを特徴とする請求項25に記載の方法。
- 前記反射層はAgを含むことを特徴とする請求項29に記載の方法。
- 支持体と、前記支持体上に配置された複数のナノワイヤとを備え、前記ナノワイヤの各々が先端部及び側壁を備えるLED構造であって、
(i)前記ナノワイヤは、第1の導電型の半導体ナノワイヤコアと、それを取り囲む第2の導電型の半導体シェルとを備え、前記コア及び前記シェルは、動作中に光を発生する活性領域を提供するpn接合又はpin接合を形成するように構成され、
(ii)前記側壁は、低導電率層と高導電率層とが交互に配置された複数の層を備え、前記先端部は、1つの低導電率層又は前記側壁の層に対応する複数の層を備え、前記先端部の層は前記側壁の層より薄いことを特徴とする構造。 - 前記側壁の低導電率層はp−AlGaNを含むことを特徴とする請求項31に記載の構造。
- 前記側壁の高導電率層はp−GaNを含むことを特徴とする請求項31又は32に記載の構造。
- 前記先端部の低導電率層はp−AlGaNを含むことを特徴とする請求項31から33のいずれか1項に記載の構造。
- 前記第1の導電型のコアは、前記支持体のバッファ層と電気的に接触していることを特徴とする請求項31から34のいずれか1項に記載の構造。
- 前記第2の導電型のシェルは、マスク層により前記バッファ層から絶縁されることを特徴とする請求項31から35のいずれか1項に記載の構造。
- 前記第1の導電型はn型であり、前記第2の導電型はp型であることを特徴とする請求項31から36のいずれか1項に記載の構造。
- 前記先端部層又は前記複数の先端部層は10〜30nmの厚さであることを特徴とする請求項31から37のいずれか1項に記載の構造。
- 支持体と、前記支持体上に配列された複数のナノワイヤとを備え、前記ナノワイヤの各々が先端部及び側壁を備えるLED構造であって、前記先端部の各々は、前記側壁の全体に沿って下方までは延設されない外側絶縁層を備えることを特徴とする構造。
- 前記絶縁層はSiOxを含むことを特徴とする請求項39に記載の構造。
- 前記SiOxはSiO2であることを特徴とする請求項40に記載の構造。
- 前記絶縁層は、2〜5%のMgを含むpGaNより成り、10〜50のV族/III族比を使用してMOCVDにより成長されることを特徴とする請求項39に記載の構造。
- 支持体と、前記支持体上に配列された複数のナノワイヤとを備え、前記ナノワイヤの各々が先端部及び側壁を備えるLED構造であって、前記ナノワイヤの各々は、第1の導電型の半導体コアと、第2の導電型の半導体シェルとを備え、前記側壁及び前記先端部は、前記第2の導電型の半導体シェルを構成し、前記ナノワイヤの各々は、前記コアと前記シェルとの間に多重量子ウェル(MQW)活性領域を構成し、前記MQW活性領域は前記側壁に近接するが、前記先端部には近接しないことを特徴とする構造。
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