JP2018074034A - 高周波装置 - Google Patents
高周波装置 Download PDFInfo
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- JP2018074034A JP2018074034A JP2016213399A JP2016213399A JP2018074034A JP 2018074034 A JP2018074034 A JP 2018074034A JP 2016213399 A JP2016213399 A JP 2016213399A JP 2016213399 A JP2016213399 A JP 2016213399A JP 2018074034 A JP2018074034 A JP 2018074034A
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- 239000004065 semiconductor Substances 0.000 claims abstract description 73
- 230000005540 biological transmission Effects 0.000 claims abstract description 47
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000009413 insulation Methods 0.000 abstract description 8
- 230000000052 comparative effect Effects 0.000 description 101
- 239000002184 metal Substances 0.000 description 16
- 229910052751 metal Inorganic materials 0.000 description 16
- 230000004048 modification Effects 0.000 description 16
- 238000012986 modification Methods 0.000 description 16
- 238000010586 diagram Methods 0.000 description 14
- 238000004088 simulation Methods 0.000 description 14
- 239000003990 capacitor Substances 0.000 description 8
- LFERELMXERXKKQ-NYTQINMXSA-N cpad Chemical compound NC(=O)C1=CC=CC([C@H]2[C@@H]([C@@H](O)[C@H](COP([O-])(=O)O[P@@](O)(=O)OC[C@H]3[C@@H]([C@@H](O)[C@@H](O3)N3C4=NC=NC(N)=C4N=C3)O)O2)O)=[NH+]1 LFERELMXERXKKQ-NYTQINMXSA-N 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000000149 penetrating effect Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004809 Teflon Substances 0.000 description 1
- 229920006362 Teflon® Polymers 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
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Abstract
【解決手段】半導体素子が形成された半導体基板と、半導体基板上に設けられた絶縁層上に設けられ、基準電位が供給される第1基準層と、絶縁層内に第1基準層に対向して設けられ、半導体素子と電気的に接続し、第1基準層とともに伝送線路を構成する信号配線と、絶縁層上であって第1基準層に設けられた開口内に第1基準層から離間して設けられ、信号配線と電気的に接続されたパッドと、絶縁層内に第1基準層に対向して設けられ、一端がパッドと電気的に接続し、他端が前記第1基準層に電気的に接続し、伝送線路で伝送される信号の波長をλとしたときλ/4未満の長さを有する付加線路と、絶縁層内に設けられ、基準電位が供給され、信号配線のうち開口に重なる部分およびパッドのうち前記パッドの中心より信号配線側の部分の少なくとも一部と重なる第2基準層と、を具備する高周波装置。
【選択図】図18
Description
最初に本願発明の実施形態の内容を列記して説明する。
(1)本願発明の一実施形態は、半導体素子が形成された半導体基板と、前記半導体基板上に設けられた絶縁層上に設けられ、基準電位が供給される第1基準層と、前記絶縁層内に前記第1基準層に対向して設けられ、前記半導体素子と電気的に接続し、前記第1基準層とともに伝送線路を構成する信号配線と、前記半導体基板上に設けられた前記絶縁層上であって前記第1基準層に設けられた開口内に前記第1基準層から離間して設けられ、前記信号配線と電気的に接続されたパッドと、前記絶縁層内に前記第1基準層に対向して設けられ、一端が前記パッドと電気的に接続し、他端が前記第1基準層に電気的に接続し、前記伝送線路で伝送される信号の波長をλとしたときλ/4未満の長さを有する付加線路と、前記絶縁層内に設けられ、前記基準電位が供給され、前記信号配線のうち前記開口に重なる部分および前記パッドのうち前記パッドの中心より前記信号配線側の部分の少なくとも一部と重なる第2基準層と、を具備する高周波装置である。付加線路と第2基準層を設けることで、伝送線路とパッドとのインピーダンス整合が改善し、反射特性が改善する。
(2)前記第2基準層は、前記信号配線を挟む両側において前記第1基準層と接続されることが好ましい。これにより、伝送線路による損失を抑制できる。
(3)前記信号配線のうち前記第2基準層に重なる部分の少なくとも一部の幅は、前記信号配線のうち前記第1基準層に重ねる部分の幅より大きいことが好ましい。これにより、反射特性をより改善できる。
(4)前記伝送線路側の前記開口の端部と前記パッドの端部との距離は、前記付加線路側の前記開口の端部と前記パッドの端部との距離より小さいことが好ましい。これにより、反射特性をより改善できる。
図1は、比較例1に係る高周波装置の断面図である。図1に示すように、実装基板20に半導体チップ10がバンプ30を用い搭載されている。半導体チップ10においては、半導体基板12上(図1では下、以下同様)に絶縁層14が形成されている。絶縁層14内に配線層16が形成されている。半導体基板12上に絶縁層14を介し金属層18が形成されている。絶縁層14の少なくとも一部を貫通するビアホール15が形成されている。ビアホール15には金属が埋め込まれている。ビアホール15は配線層16間を電気的に接続する、または配線層16と金属層18とを電気的に接続する。配線層16は信号配線34を含む。信号配線34は、半導体基板12に形成された半導体素子に電気的に接続される。金属層18は基準層32およびパッド36を含む。基準層32には、グランド電位等の基準電位(例えば直流電位)が供給される。基準層32と信号配線34とは対向して設けられ、伝送線路33を形成する。伝送線路33はマイクロストリップラインである。
図4は、比較例2における半導体チップをバンプ側からみた平面図である。図4に示すように、比較例2においては、付加配線38および配線15hが設けられていない。その他の構成は比較例1と同じであり説明を省略する。
比較例1では、 付加配線38は基準層32に対向して設けられている。付加配線38の一端が配線15gを介してパッド36と電気的に接続され、他端が配線15hを介して基準層32に電気的に接続されている。これにより、付加配線38、配線15gおよび15hを含むパッド36から基準層32までのラインが、ショートスタブとして機能する。ただし、配線15gおよび15hは付加配線38に比べ非常に短いため、付加配線38の長さが実質的にショートスタブの長さとなる。付加配線38は、伝送線路33を伝送する高周波信号の波長をλとしたとき、λ/4未満の長さとする。これにより、付加配線38は高周波信号にインダクタとしてみえる。パッド36の基準層32に対するキャパシタンスをCpadとし、付加配線38によるインダクタンスをLstubとする。このとき、CpadとLstubによる基準層32に対するキャパシタンスCtotalは次式となる。
Ctotal=Cpad−1/(ω2Lstub)
主に付加配線38の長さを調整することにより、Ctotalを調整することができる。これにより、パッド36と伝送線路33との間のインピーダンス不整合を抑制できる。よって、パッド36およびバンプ30による高周波信号の反射を抑制できる。
半導体基板12:GaAs基板、膜厚H12=250μm
絶縁層14:ポリイミド、比誘電率3.5、膜厚H14=8μm
金属層18:金、膜厚H18=2μm
バンプ30:はんだ:膜厚H30=100μm、幅W30=150μm、ピッチW31=400μm
信号配線34:特性インピーダンス50Ω、幅W34=10μm
開口35:幅W35=250μm
パッド36:幅W36=150μm
付加配線38:特性インピーダンス50Ω、幅W38=10μm、長さL38=250μm
基板22:テフロン(登録商標)、膜厚H22=101μm
レジスト24:膜厚H24=30μm
ビアホール25:銅、幅W25=100μm
金属層28:銅、膜厚H24=30μm
信号配線44:特性インピーダンス50Ω、幅W44=190μm
切り込み45:幅W45=100μm
パッド46:幅W46=250μm
次に、比較例1および比較例2について信号配線44からみた反射特性S11についてシミュレーションした。シミュレーションには、例示した材料および寸法を用いた。図5(a)および図5(b)は、比較例1および2におけるシミュレーションに用いた等価回路を示す図である。図5(a)および図5(b)に示すように、バンプ30はインダクタ1、インダクタ2およびキャパシタC1により等価的に表した。インダクタ1およびインダクタ2はパッド36と46との間に直列に接続されている。キャパシタC1は、インダクタ1とインダクタ2との間のノードと基準電位との間に接続されている。インダクタ1およびインダクタ2のインダクタンスを各々5pH、キャパシタC1のキャパシタンスを15pFとした。
比較例1 S11=−7.4dB
L38=50μm S11=−6.9dB
L38=100μm S11=−7.3dB
L38=250μm S11=−7.9dB
L38=400μm S11=−7.9dB
L38=500μm S11=−7.0dB
付加配線38の長さL38を250μmおよび400μmとしてもS11は比較例1から0.5dBの改善にとどまる。
そこで、信号配線の幅を広くすることが考えられる。図10は、比較例3における半導体チップをバンプ側からみた平面図である。図10に示すように、パッド36から信号配線34が引き出される引き出し部において、幅広配線34cが設けられている。幅広配線34cの長さL34cおよび幅W34cである。幅広配線34cの幅W34cと信号配線の幅W34との間では、幅がテーパ状に小さくなる。
幅広配線34c:幅W34c=100μm、長さL34c=30μm
付加配線38:特性インピーダンス50Ω、幅W38=10μm、長さL38=60μm
その他のシミュレーション条件は比較例1と同じであり説明を省略する。
85GHzのS11は、以下である。
比較例1 S11=−7.92dB
比較例2 S11=−7.36dB
比較例3 S11=−11.59dB
このように、比較例3により、S11を4dB改善できた。
比較例3の代わりに、信号配線側の開口の幅を狭くすることが考えられる。図14は、比較例4における半導体チップをバンプ側からみた平面図である。図14に示すように、パッド36から付加配線38が引き出される箇所における開口35の端部とパッド36の端部との距離をW35aとする。パッド36から伝送線路33が引き出される箇所における開口35の端部とパッド36の端部の距離W35bとする。距離W35bはW35aより小さい。開口35の端部とパッド36の端部との距離は伝送線路33の引き出し箇所近傍でのみ小さく、他の箇所ではほぼ一定である。その他の構成は比較例1と同じであり説明を省略する。
距離W35a:50μm
距離W35b:10μm
その他のシミュレーション条件は比較例1と同じであり説明を省略する。
基準層37の幅W37:35μm
その他のシミュレーション条件は比較例1と同じであり説明を省略する。
12 半導体基板
14、14a−14d 絶縁層
15、15b−15f、15i−15j ビアホール
15a、15h、15g 配線
16、16a−16d 配線層
18 金属層
20 実装基板
22 基板
24 レジスト
25 ビアホール
26 基準層
28 金属層
30、30a−30c バンプ
32 基準層
33 伝送線路
34、34a、34b、34d 信号配線
34c 幅広配線
35、35a−35c 開口
36,36a−36c パッド
37、37a、37b 基準層
38、38a−38c 付加線路
42 基準層
43、43c 伝送線路
44、44c 信号配線
45 切り込み
46、46a、46b パッド
50 半導体素子
Claims (4)
- 半導体素子が形成された半導体基板と、
前記半導体基板上に設けられた絶縁層上に設けられ、基準電位が供給される第1基準層と、
前記絶縁層内に前記第1基準層に対向して設けられ、前記半導体素子と電気的に接続し、前記第1基準層とともに伝送線路を構成する信号配線と、
前記半導体基板上に設けられた前記絶縁層上であって前記第1基準層に設けられた開口内に前記第1基準層から離間して設けられ、前記信号配線と電気的に接続されたパッドと、
前記絶縁層内に前記第1基準層に対向して設けられ、一端が前記パッドと電気的に接続し、他端が前記第1基準層に電気的に接続し、前記伝送線路で伝送される信号の波長をλとしたときλ/4未満の長さを有する付加線路と、
前記絶縁層内に設けられ、前記基準電位が供給され、前記信号配線のうち前記開口に重なる部分および前記パッドのうち前記パッドの中心より前記信号配線側の部分の少なくとも一部と重なる第2基準層と、
を具備する高周波装置。 - 前記第2基準層は、前記信号配線を挟む両側において前記第1基準層と接続される請求項1記載の高周波装置。
- 前記信号配線のうち前記第2基準層に重なる部分の少なくとも一部の幅は、前記信号配線のうち前記第1基準層に重ねる部分の幅より大きい請求項1または2に記載の高周波装置。
- 前記伝送線路側の前記開口の端部と前記パッドの端部との距離は、前記付加線路側の前記開口の端部と前記パッドの端部との距離より小さい請求項1から3のいずれか一項に記載の高周波装置。
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07170114A (ja) * | 1993-12-16 | 1995-07-04 | Sharp Corp | マイクロ波回路 |
JPH11168307A (ja) * | 1997-12-05 | 1999-06-22 | Denso Corp | マイクロ波集積回路 |
JP2003188606A (ja) * | 2001-12-13 | 2003-07-04 | Mitsubishi Electric Corp | 振幅補償回路 |
JP2007134359A (ja) * | 2005-11-08 | 2007-05-31 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
US20100214041A1 (en) * | 2009-02-25 | 2010-08-26 | Shu-Ying Cho | Coupled Microstrip Lines with Tunable Characteristic Impedance and Wavelength |
JP2011096954A (ja) * | 2009-10-30 | 2011-05-12 | Kyocer Slc Technologies Corp | 配線基板 |
WO2015005028A1 (ja) * | 2013-07-09 | 2015-01-15 | 株式会社村田製作所 | 高周波伝送線路 |
JP2015050678A (ja) * | 2013-09-03 | 2015-03-16 | 日本電信電話株式会社 | 高周波伝送線路 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6204448B1 (en) * | 1998-12-04 | 2001-03-20 | Kyocera America, Inc. | High frequency microwave packaging having a dielectric gap |
US6674174B2 (en) * | 2001-11-13 | 2004-01-06 | Skyworks Solutions, Inc. | Controlled impedance transmission lines in a redistribution layer |
US6730540B2 (en) * | 2002-04-18 | 2004-05-04 | Tru-Si Technologies, Inc. | Clock distribution networks and conductive lines in semiconductor integrated circuits |
JP4299760B2 (ja) * | 2004-10-21 | 2009-07-22 | エルピーダメモリ株式会社 | 半導体装置のテスト方法 |
US7773390B2 (en) * | 2006-06-06 | 2010-08-10 | Teraspeed Consulting Group Llc | Power distribution system for integrated circuits |
US7886431B2 (en) * | 2006-06-06 | 2011-02-15 | Teraspeed Consulting Group Llc | Power distribution system for integrated circuits |
US8946873B2 (en) * | 2007-08-28 | 2015-02-03 | Micron Technology, Inc. | Redistribution structures for microfeature workpieces |
TW200941601A (en) * | 2008-03-19 | 2009-10-01 | Chipmos Technologies Inc | Conductive structure of a chip |
US8830690B2 (en) * | 2008-09-25 | 2014-09-09 | International Business Machines Corporation | Minimizing plating stub reflections in a chip package using capacitance |
US9171798B2 (en) * | 2013-01-25 | 2015-10-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Methods and apparatus for transmission lines in packages |
US9761571B2 (en) * | 2015-09-17 | 2017-09-12 | Deca Technologies Inc. | Thermally enhanced fully molded fan-out module |
DE112017007145T5 (de) * | 2017-04-07 | 2019-11-28 | Mitsubishi Electric Corporation | Zwischenplattenverbindungsstruktur |
US11004812B2 (en) * | 2018-09-18 | 2021-05-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structure and method of forming the same |
US11244908B2 (en) * | 2018-11-06 | 2022-02-08 | STATS ChipPAC Pte. Ltd. | Method and device for reducing metal burrs when sawing semiconductor packages |
-
2016
- 2016-10-31 JP JP2016213399A patent/JP6798252B2/ja active Active
-
2017
- 2017-10-30 US US15/797,944 patent/US20180122755A1/en not_active Abandoned
-
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- 2020-11-25 US US17/105,492 patent/US20210151396A1/en not_active Abandoned
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07170114A (ja) * | 1993-12-16 | 1995-07-04 | Sharp Corp | マイクロ波回路 |
JPH11168307A (ja) * | 1997-12-05 | 1999-06-22 | Denso Corp | マイクロ波集積回路 |
JP2003188606A (ja) * | 2001-12-13 | 2003-07-04 | Mitsubishi Electric Corp | 振幅補償回路 |
JP2007134359A (ja) * | 2005-11-08 | 2007-05-31 | Casio Comput Co Ltd | 半導体装置およびその製造方法 |
US20100214041A1 (en) * | 2009-02-25 | 2010-08-26 | Shu-Ying Cho | Coupled Microstrip Lines with Tunable Characteristic Impedance and Wavelength |
JP2011096954A (ja) * | 2009-10-30 | 2011-05-12 | Kyocer Slc Technologies Corp | 配線基板 |
WO2015005028A1 (ja) * | 2013-07-09 | 2015-01-15 | 株式会社村田製作所 | 高周波伝送線路 |
JP2015050678A (ja) * | 2013-09-03 | 2015-03-16 | 日本電信電話株式会社 | 高周波伝送線路 |
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