JP2018073452A5 - - Google Patents

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Publication number
JP2018073452A5
JP2018073452A5 JP2017193447A JP2017193447A JP2018073452A5 JP 2018073452 A5 JP2018073452 A5 JP 2018073452A5 JP 2017193447 A JP2017193447 A JP 2017193447A JP 2017193447 A JP2017193447 A JP 2017193447A JP 2018073452 A5 JP2018073452 A5 JP 2018073452A5
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Japan
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column
computing
dram
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columns
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JP2017193447A
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Japanese (ja)
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JP6785738B2 (ja
JP2018073452A (ja
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Priority claimed from US15/425,996 external-priority patent/US9922696B1/en
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JP2017193447A 2016-10-28 2017-10-03 Ｄｒａｍ基盤のプロセシングユニット Active JP6785738B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201662414426P 2016-10-28 2016-10-28
US62/414,426 2016-10-28
US15/425,996 US9922696B1 (en) 2016-10-28 2017-02-06 Circuits and micro-architecture for a DRAM-based processing unit
US15/425,996 2017-02-06

Publications (3)

Publication Number Publication Date
JP2018073452A JP2018073452A (ja) 2018-05-10
JP2018073452A5 true JP2018073452A5 (enExample) 2020-10-22
JP6785738B2 JP6785738B2 (ja) 2020-11-18

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JP2017193447A Active JP6785738B2 (ja) 2016-10-28 2017-10-03 Ｄｒａｍ基盤のプロセシングユニット

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US (1) US9922696B1 (enExample)
JP (1) JP6785738B2 (enExample)
KR (1) KR102182217B1 (enExample)
CN (1) CN108022615B (enExample)
TW (1) TWI713047B (enExample)

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KR20250145258A (ko) 2024-03-28 2025-10-13 경희대학교 산학협력단 Dram의 비트 단위 논리 연산을 수행하는 pim 연산 장치 및 pim 연산 방법

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