JP2016123092A5 - - Google Patents

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Publication number
JP2016123092A5
JP2016123092A5 JP2015245493A JP2015245493A JP2016123092A5 JP 2016123092 A5 JP2016123092 A5 JP 2016123092A5 JP 2015245493 A JP2015245493 A JP 2015245493A JP 2015245493 A JP2015245493 A JP 2015245493A JP 2016123092 A5 JP2016123092 A5 JP 2016123092A5
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Japan
Prior art keywords
reconfigurable
lookup table
logic device
memory
logical function
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JP2015245493A
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English (en)
Japanese (ja)
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JP6594762B2 (ja
JP2016123092A (ja
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Priority claimed from US14/814,503 external-priority patent/US9954533B2/en
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JP2015245493A 2014-12-16 2015-12-16 Dram基盤の再構成可能なロジック装置及び方法 Active JP6594762B2 (ja)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US201462092822P 2014-12-16 2014-12-16
US201462092825P 2014-12-16 2014-12-16
US201462092819P 2014-12-16 2014-12-16
US62/092825 2014-12-16
US62/092819 2014-12-16
US62/092822 2014-12-16
US14/814,503 US9954533B2 (en) 2014-12-16 2015-07-30 DRAM-based reconfigurable logic
US14/814503 2015-07-30

Publications (3)

Publication Number Publication Date
JP2016123092A JP2016123092A (ja) 2016-07-07
JP2016123092A5 true JP2016123092A5 (enExample) 2019-01-31
JP6594762B2 JP6594762B2 (ja) 2019-10-23

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JP2015245493A Active JP6594762B2 (ja) 2014-12-16 2015-12-16 Dram基盤の再構成可能なロジック装置及び方法

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US (3) US9954533B2 (enExample)
JP (1) JP6594762B2 (enExample)
KR (3) KR102496680B1 (enExample)
CN (1) CN105703765B (enExample)
TW (1) TWI649970B (enExample)

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