KR102496680B1 - 디램-기반의 재설정 가능 로직 - Google Patents

디램-기반의 재설정 가능 로직 Download PDF

Info

Publication number
KR102496680B1
KR102496680B1 KR1020150179353A KR20150179353A KR102496680B1 KR 102496680 B1 KR102496680 B1 KR 102496680B1 KR 1020150179353 A KR1020150179353 A KR 1020150179353A KR 20150179353 A KR20150179353 A KR 20150179353A KR 102496680 B1 KR102496680 B1 KR 102496680B1
Authority
KR
South Korea
Prior art keywords
lookup table
memory
reconfigurable
resettable
memory array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020150179353A
Other languages
English (en)
Korean (ko)
Other versions
KR20160073324A (ko
Inventor
밍위 가오
홍종 정
크리슈나 티. 말라디
Original Assignee
삼성전자주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 삼성전자주식회사 filed Critical 삼성전자주식회사
Publication of KR20160073324A publication Critical patent/KR20160073324A/ko
Application granted granted Critical
Publication of KR102496680B1 publication Critical patent/KR102496680B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748Structural details of configuration resources
    • H03K19/1776Structural details of configuration resources for memories
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/18Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of the types provided for in two or more different main groups of the same subclass of H10B, H10D, H10F, H10H, H10K or H10N
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of semiconductor or other solid state devices
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17724Structural details of logic blocks
    • H03K19/17728Reconfigurable logic blocks, e.g. lookup tables
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736Structural details of routing resources
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17748Structural details of configuration resources
    • H03K19/17758Structural details of configuration resources for speeding up configuration or reconfiguration
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Manufacturing & Machinery (AREA)
  • Logic Circuits (AREA)
  • Microcomputers (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
KR1020150179353A 2014-12-16 2015-12-15 디램-기반의 재설정 가능 로직 Active KR102496680B1 (ko)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US201462092819P 2014-12-16 2014-12-16
US201462092825P 2014-12-16 2014-12-16
US201462092822P 2014-12-16 2014-12-16
US62/092,822 2014-12-16
US62/092,819 2014-12-16
US62/092,825 2014-12-16
US14/814,503 US9954533B2 (en) 2014-12-16 2015-07-30 DRAM-based reconfigurable logic
US14/814,503 2015-07-30

Publications (2)

Publication Number Publication Date
KR20160073324A KR20160073324A (ko) 2016-06-24
KR102496680B1 true KR102496680B1 (ko) 2023-02-06

Family

ID=56112171

Family Applications (3)

Application Number Title Priority Date Filing Date
KR1020150179353A Active KR102496680B1 (ko) 2014-12-16 2015-12-15 디램-기반의 재설정 가능 로직
KR1020150180208A Active KR102440132B1 (ko) 2014-12-16 2015-12-16 재설정 가능 논리 장치
KR1020150180209A Active KR102438730B1 (ko) 2014-12-16 2015-12-16 공간 다중화를 지원하는 디램 기초의 재설정 가능 논리 장치

Family Applications After (2)

Application Number Title Priority Date Filing Date
KR1020150180208A Active KR102440132B1 (ko) 2014-12-16 2015-12-16 재설정 가능 논리 장치
KR1020150180209A Active KR102438730B1 (ko) 2014-12-16 2015-12-16 공간 다중화를 지원하는 디램 기초의 재설정 가능 논리 장치

Country Status (5)

Country Link
US (3) US9954533B2 (enExample)
JP (1) JP6594762B2 (enExample)
KR (3) KR102496680B1 (enExample)
CN (1) CN105703765B (enExample)
TW (1) TWI649970B (enExample)

Families Citing this family (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10013212B2 (en) * 2015-11-30 2018-07-03 Samsung Electronics Co., Ltd. System architecture with memory channel DRAM FPGA module
US10075168B2 (en) * 2016-03-05 2018-09-11 XiaMen HaiCun IP Technology LLC Configurable computing array comprising three-dimensional writable memory
US20170323041A1 (en) * 2016-05-04 2017-11-09 Chengdu Haicun Ip Technology Llc Simulation Processor with In-Package Look-Up Table
US10848158B2 (en) 2016-02-13 2020-11-24 HangZhou HaiCun Information Technology Co., Ltd. Configurable processor
JP2017169118A (ja) * 2016-03-17 2017-09-21 株式会社東芝 集積回路および電子機器
CN107346230A (zh) * 2016-05-04 2017-11-14 杭州海存信息技术有限公司 基于封装内查找表的处理器
US9871020B1 (en) * 2016-07-14 2018-01-16 Globalfoundries Inc. Through silicon via sharing in a 3D integrated circuit
US11361813B2 (en) 2016-09-16 2022-06-14 Aspiring Sky Co. Limited Nonvolatile memory structures with DRAM
US10354716B2 (en) 2016-09-16 2019-07-16 Aspiring Sky Co. Limited SRAM based memory structures and methods thereof
US10353715B2 (en) 2016-10-20 2019-07-16 Aspiring Sky Co. Limited Low power non-volatile SRAM memory systems
US10402342B2 (en) * 2016-10-20 2019-09-03 Aspiring Sky Co., Limited Re-configurable non-volatile memory structures and systems
US10242728B2 (en) * 2016-10-27 2019-03-26 Samsung Electronics Co., Ltd. DPU architecture
US10732866B2 (en) 2016-10-27 2020-08-04 Samsung Electronics Co., Ltd. Scaling out architecture for DRAM-based processing unit (DPU)
US10180808B2 (en) * 2016-10-27 2019-01-15 Samsung Electronics Co., Ltd. Software stack and programming for DPU operations
US9922696B1 (en) 2016-10-28 2018-03-20 Samsung Electronics Co., Ltd. Circuits and micro-architecture for a DRAM-based processing unit
US10386410B2 (en) * 2016-12-12 2019-08-20 Samsung Electronics Co., Ltd. Highly flexible performance counter and system debug module
US10489544B2 (en) 2016-12-14 2019-11-26 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
US11625523B2 (en) 2016-12-14 2023-04-11 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips
KR102245385B1 (ko) * 2017-03-28 2021-04-27 에스케이하이닉스 주식회사 자기 소자를 포함하는 lut, 이를 포함하는 fpga 및 기술 매핑 방법
US10447274B2 (en) 2017-07-11 2019-10-15 iCometrue Company Ltd. Logic drive based on standard commodity FPGA IC chips using non-volatile memory cells
US10957679B2 (en) 2017-08-08 2021-03-23 iCometrue Company Ltd. Logic drive based on standardized commodity programmable logic semiconductor IC chips
US10630296B2 (en) 2017-09-12 2020-04-21 iCometrue Company Ltd. Logic drive with brain-like elasticity and integrality based on standard commodity FPGA IC chips using non-volatile memory cells
US11119677B2 (en) 2017-12-15 2021-09-14 Samsung Electronics Co., Ltd. HBM based memory lookup engine for deep learning accelerator
US10628295B2 (en) 2017-12-26 2020-04-21 Samsung Electronics Co., Ltd. Computing mechanisms using lookup tables stored on memory
US11398453B2 (en) * 2018-01-09 2022-07-26 Samsung Electronics Co., Ltd. HBM silicon photonic TSV architecture for lookup computing AI accelerator
US10732929B2 (en) * 2018-01-09 2020-08-04 Samsung Electronics Co., Ltd. Computing accelerator using a lookup table
US10608642B2 (en) * 2018-02-01 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile radom access memory cells
US10623000B2 (en) 2018-02-14 2020-04-14 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US10608638B2 (en) * 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US12476637B2 (en) * 2018-05-24 2025-11-18 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
US11309334B2 (en) 2018-09-11 2022-04-19 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US10892011B2 (en) 2018-09-11 2021-01-12 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips comprising non-volatile random access memory cells
US10937762B2 (en) 2018-10-04 2021-03-02 iCometrue Company Ltd. Logic drive based on multichip package using interconnection bridge
US11616046B2 (en) 2018-11-02 2023-03-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US11211334B2 (en) 2018-11-18 2021-12-28 iCometrue Company Ltd. Logic drive based on chip scale package comprising standardized commodity programmable logic IC chip and memory IC chip
US10985154B2 (en) 2019-07-02 2021-04-20 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cryptography circuits
US11227838B2 (en) 2019-07-02 2022-01-18 iCometrue Company Ltd. Logic drive based on multichip package comprising standard commodity FPGA IC chip with cooperating or supporting circuits
KR102322727B1 (ko) * 2019-07-29 2021-11-05 에스케이하이닉스 주식회사 데이터 스왑을 위한 메모리 시스템 및 그 동작방법
US11887930B2 (en) 2019-08-05 2024-01-30 iCometrue Company Ltd. Vertical interconnect elevator based on through silicon vias
US11637056B2 (en) 2019-09-20 2023-04-25 iCometrue Company Ltd. 3D chip package based on through-silicon-via interconnection elevator
US11600526B2 (en) 2020-01-22 2023-03-07 iCometrue Company Ltd. Chip package based on through-silicon-via connector and silicon interconnection bridge
US11403111B2 (en) 2020-07-17 2022-08-02 Micron Technology, Inc. Reconfigurable processing-in-memory logic using look-up tables
US11355170B1 (en) 2020-12-16 2022-06-07 Micron Technology, Inc. Reconfigurable processing-in-memory logic
US12176278B2 (en) 2021-05-30 2024-12-24 iCometrue Company Ltd. 3D chip package based on vertical-through-via connector
US12112792B2 (en) 2021-08-10 2024-10-08 Micron Technology, Inc. Memory device for wafer-on-wafer formed memory and logic
US12268012B2 (en) 2021-09-24 2025-04-01 iCometrue Company Ltd. Multi-output look-up table (LUT) for use in coarse-grained field-programmable-gate-array (FPGA) integrated-circuit (IC) chip

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002538652A (ja) * 1999-02-25 2002-11-12 ザイリンクス インコーポレイテッド 多目的論理/メモリ回路を具備するfpga形態特定可能論理ブロック
JP2004529576A (ja) 2001-05-16 2004-09-24 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 再構成可能な論理デバイス
US20140244981A1 (en) 2013-02-26 2014-08-28 Fujitsu Semiconductor Limited Processor and control method for processor

Family Cites Families (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5633830A (en) * 1995-11-08 1997-05-27 Altera Corporation Random access memory block circuitry for programmable logic array integrated circuit devices
US5260610A (en) * 1991-09-03 1993-11-09 Altera Corporation Programmable logic element interconnections for programmable logic array integrated circuits
GB9303084D0 (en) * 1993-02-16 1993-03-31 Inmos Ltd Programmable logic circuit
EP0689712A4 (en) * 1993-03-17 1997-05-28 Zycad Corp CONFIGURABLE FIELDS WITH DIRECT ACCESS MEMORY ARRANGEMENT
US5689195A (en) * 1995-05-17 1997-11-18 Altera Corporation Programmable logic array integrated circuit devices
GB9604496D0 (en) * 1996-03-01 1996-05-01 Xilinx Inc Embedded memory for field programmable gate array
US6020759A (en) * 1997-03-21 2000-02-01 Altera Corporation Programmable logic array device with random access memory configurable as product terms
JP3106998B2 (ja) * 1997-04-11 2000-11-06 日本電気株式会社 メモリ付加型プログラマブルロジックlsi
JPH11220382A (ja) * 1997-11-03 1999-08-10 Altera Corp 内容アドレス可能埋め込みアレイ・ブロックを組み込んだプログラマブル論理アーキテクチャ
DE69815482T2 (de) 1997-12-24 2004-04-29 Texas Instruments Inc., Dallas Computer Anordnung mit Prozessor und Speicher-Hierarchie und sein Betriebsverfahren
US6184712B1 (en) * 1999-02-25 2001-02-06 Xilinx, Inc. FPGA configurable logic block with multi-purpose logic/memory circuit
JP3743487B2 (ja) * 1999-07-14 2006-02-08 富士ゼロックス株式会社 プログラマブル論理回路装置、情報処理システム、プログラマブル論理回路装置への回路の再構成方法、プログラマブル論理回路装置用の回路情報の圧縮方法
US6627985B2 (en) * 2001-12-05 2003-09-30 Arbor Company Llp Reconfigurable processor module comprising hybrid stacked integrated circuit die elements
JP4260026B2 (ja) * 2002-03-18 2009-04-30 エヌエックスピー ビー ヴィ リコンフィギャラブル・ロジックにおける大型マルチプレクサの実現
EP1597825B1 (en) * 2003-02-19 2007-06-06 Koninklijke Philips Electronics N.V. Electronic circuit with array of programmable logic cells
US6934174B2 (en) * 2003-09-03 2005-08-23 Lsi Logic Corporation Reconfigurable memory arrays
US7129749B1 (en) * 2004-10-27 2006-10-31 Lattice Semiconductor Corporation Programmable logic device having a configurable DRAM with transparent refresh
US7468993B2 (en) 2005-01-14 2008-12-23 International Business Machines Corporation Dynamic reconfiguration of solid state memory device to replicate and time multiplex data over multiple data interfaces
JP4191219B2 (ja) * 2006-10-30 2008-12-03 エルピーダメモリ株式会社 メモリ回路、半導体装置及びメモリ回路の制御方法
JP4215795B2 (ja) * 2006-11-20 2009-01-28 エルピーダメモリ株式会社 ルックアップテーブルカスケード回路、ルックアップテーブルカスケードアレイ回路及びそのパイプライン制御方法
US20080162856A1 (en) 2006-12-29 2008-07-03 Motorola, Inc. Method for dynamic memory allocation on reconfigurable logic
US8112468B1 (en) * 2007-03-22 2012-02-07 Tabula, Inc. Method and apparatus for performing an operation with a plurality of sub-operations in a configurable IC
GB2455806B (en) * 2007-12-21 2010-04-14 Wolfson Microelectronics Plc Filter
US8254191B2 (en) * 2008-10-30 2012-08-28 Micron Technology, Inc. Switched interface stacked-die memory architecture
CN101847970A (zh) * 2010-04-29 2010-09-29 复旦大学 一种功能可重构的数字系统
WO2014080872A2 (ja) * 2012-11-20 2014-05-30 太陽誘電株式会社 再構成可能な半導体装置の論理構成方法
TWI636667B (zh) * 2013-04-02 2018-09-21 Taiyo Yuden Co., Ltd. 可再構成之邏輯元件
CN104575595B (zh) * 2014-12-12 2017-07-07 杭州华澜微电子股份有限公司 非易失性随机存取的存储装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002538652A (ja) * 1999-02-25 2002-11-12 ザイリンクス インコーポレイテッド 多目的論理/メモリ回路を具備するfpga形態特定可能論理ブロック
JP2004529576A (ja) 2001-05-16 2004-09-24 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ 再構成可能な論理デバイス
US20140244981A1 (en) 2013-02-26 2014-08-28 Fujitsu Semiconductor Limited Processor and control method for processor

Also Published As

Publication number Publication date
KR102438730B1 (ko) 2022-08-31
TWI649970B (zh) 2019-02-01
KR20160073335A (ko) 2016-06-24
TW201633718A (zh) 2016-09-16
KR20160073334A (ko) 2016-06-24
US20160173103A1 (en) 2016-06-16
KR102440132B1 (ko) 2022-09-05
CN105703765A (zh) 2016-06-22
US9577644B2 (en) 2017-02-21
US20160173101A1 (en) 2016-06-16
CN105703765B (zh) 2020-10-09
US9954533B2 (en) 2018-04-24
KR20160073324A (ko) 2016-06-24
JP2016123092A (ja) 2016-07-07
JP6594762B2 (ja) 2019-10-23
US20160173102A1 (en) 2016-06-16
US9503095B2 (en) 2016-11-22

Similar Documents

Publication Publication Date Title
KR102496680B1 (ko) 디램-기반의 재설정 가능 로직
JP6738262B2 (ja) 加速器コントローラ及びその加速器ロジックローディング方法
US9214209B2 (en) Semiconductor device
KR102500357B1 (ko) 메모리 로드 및 산술 로드 유닛 융합
US20200133632A1 (en) Selecting an ith largest or a pth smallest number from a set of n m-bit numbers
US11163530B2 (en) Programmable-logic-directed multiplier mapping
US20240028295A1 (en) Efficient logic blocks architectures for dense mapping of multipliers
US10564963B2 (en) Bit-masked variable-precision barrel shifter
US11467804B2 (en) Geometric synthesis

Legal Events

Date Code Title Description
PA0109 Patent application

Patent event code: PA01091R01D

Comment text: Patent Application

Patent event date: 20151215

PG1501 Laying open of application
A201 Request for examination
PA0201 Request for examination

Patent event code: PA02012R01D

Patent event date: 20201215

Comment text: Request for Examination of Application

Patent event code: PA02011R01I

Patent event date: 20151215

Comment text: Patent Application

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

Comment text: Notification of reason for refusal

Patent event date: 20220214

Patent event code: PE09021S01D

E90F Notification of reason for final refusal
PE0902 Notice of grounds for rejection

Comment text: Final Notice of Reason for Refusal

Patent event date: 20220613

Patent event code: PE09021S02D

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

Patent event code: PE07011S01D

Comment text: Decision to Grant Registration

Patent event date: 20221107

GRNT Written decision to grant
PR0701 Registration of establishment

Comment text: Registration of Establishment

Patent event date: 20230201

Patent event code: PR07011E01D

PR1002 Payment of registration fee

Payment date: 20230202

End annual number: 3

Start annual number: 1

PG1601 Publication of registration