ATE458310T1 - Implementierung von breiten multiplexern in einer rekonfigurierbaren logischen vorrichtung - Google Patents

Implementierung von breiten multiplexern in einer rekonfigurierbaren logischen vorrichtung

Info

Publication number
ATE458310T1
ATE458310T1 AT03744472T AT03744472T ATE458310T1 AT E458310 T1 ATE458310 T1 AT E458310T1 AT 03744472 T AT03744472 T AT 03744472T AT 03744472 T AT03744472 T AT 03744472T AT E458310 T1 ATE458310 T1 AT E458310T1
Authority
AT
Austria
Prior art keywords
signals
implementation
output
logical device
reconfigurable logical
Prior art date
Application number
AT03744472T
Other languages
English (en)
Inventor
Katarzyna Leijten-Nowak
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE458310T1 publication Critical patent/ATE458310T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H03K19/1737—Controllable logic circuits using multiplexers

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Electronic Switches (AREA)
AT03744472T 2002-03-18 2003-03-17 Implementierung von breiten multiplexern in einer rekonfigurierbaren logischen vorrichtung ATE458310T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02076049 2002-03-18
PCT/IB2003/000967 WO2003079550A2 (en) 2002-03-18 2003-03-17 Implementation of wide multiplexers in reconfigurable logic

Publications (1)

Publication Number Publication Date
ATE458310T1 true ATE458310T1 (de) 2010-03-15

Family

ID=27838094

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03744472T ATE458310T1 (de) 2002-03-18 2003-03-17 Implementierung von breiten multiplexern in einer rekonfigurierbaren logischen vorrichtung

Country Status (8)

Country Link
US (1) US8082284B2 (de)
EP (1) EP1488523B1 (de)
JP (1) JP4260026B2 (de)
CN (1) CN1295879C (de)
AT (1) ATE458310T1 (de)
AU (1) AU2003209576A1 (de)
DE (1) DE60331296D1 (de)
WO (1) WO2003079550A2 (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004045527B4 (de) * 2003-10-08 2009-12-03 Siemens Ag Konfigurierbare Logikschaltungsanordnung
CN102147720B (zh) * 2011-03-18 2014-04-09 深圳市国微电子有限公司 用查找表实现多输入逻辑项之间的运算的装置及方法
US9450585B2 (en) * 2011-04-20 2016-09-20 Microchip Technology Incorporated Selecting four signals from sixteen inputs
CN105191139B (zh) * 2013-04-02 2018-12-07 太阳诱电株式会社 可重构逻辑器件
US9954533B2 (en) * 2014-12-16 2018-04-24 Samsung Electronics Co., Ltd. DRAM-based reconfigurable logic
JP6653126B2 (ja) * 2015-04-28 2020-02-26 太陽誘電株式会社 再構成可能な半導体装置

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5225719A (en) * 1985-03-29 1993-07-06 Advanced Micro Devices, Inc. Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix
US5233539A (en) * 1989-08-15 1993-08-03 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
US5498975A (en) * 1992-11-19 1996-03-12 Altera Corporation Implementation of redundancy on a programmable logic device
JP3127654B2 (ja) * 1993-03-12 2001-01-29 株式会社デンソー 乗除算器
JPH06276086A (ja) * 1993-03-18 1994-09-30 Fuji Xerox Co Ltd フィールドプログラマブルゲートアレイ
US5426379A (en) * 1994-07-29 1995-06-20 Xilinx, Inc. Field programmable gate array with built-in bitstream data expansion
US5442306A (en) 1994-09-09 1995-08-15 At&T Corp. Field programmable gate array using look-up tables, multiplexers and decoders
JPH09181598A (ja) 1995-12-18 1997-07-11 At & T Corp フィールドプログラマブルゲートアレイ
US6154049A (en) * 1998-03-27 2000-11-28 Xilinx, Inc. Multiplier fabric for use in field programmable gate arrays
WO1999031574A1 (en) * 1997-12-17 1999-06-24 Hewlett-Packard Company Implementation of multipliers in programmable arrays
GB9727414D0 (en) * 1997-12-29 1998-02-25 Imperial College Logic circuit
JP3123977B2 (ja) * 1998-06-04 2001-01-15 日本電気株式会社 プログラマブル機能ブロック
US6118300A (en) * 1998-11-24 2000-09-12 Xilinx, Inc. Method for implementing large multiplexers with FPGA lookup tables
JP3269526B2 (ja) 1999-02-09 2002-03-25 日本電気株式会社 プログラマブルロジックｌｓｉ
US6556042B1 (en) * 2002-02-20 2003-04-29 Xilinx, Inc. FPGA with improved structure for implementing large multiplexers
US6816562B2 (en) * 2003-01-07 2004-11-09 Mathstar, Inc. Silicon object array with unidirectional segmented bus architecture

Also Published As

Publication number Publication date
AU2003209576A1 (en) 2003-09-29
US20050232297A1 (en) 2005-10-20
EP1488523A2 (de) 2004-12-22
US8082284B2 (en) 2011-12-20
JP2005521288A (ja) 2005-07-14
WO2003079550A3 (en) 2004-03-04
CN1295879C (zh) 2007-01-17
JP4260026B2 (ja) 2009-04-30
WO2003079550A2 (en) 2003-09-25
DE60331296D1 (de) 2010-04-01
EP1488523B1 (de) 2010-02-17
CN1643793A (zh) 2005-07-20

Similar Documents

Publication Publication Date Title
WO2002079990A3 (en) Apparatus and methods for fault-tolerant computing using a switching fabric
TW200625239A (en) Methods and systems to control electronic display brightness
TW200618476A (en) Flip flop circuit & same with scan function
GB2413416B8 (en) Haptic massaging in handheld communication devices
ATE255795T1 (de) Einrichtung zur eingabe von informationen
ATE441293T1 (de) Bass-management-systeme
ATE526792T1 (de) Rekonfigurierbare hörhilfevorrichtung mit niedrigem leistungsverbrauch
AU2003240534A1 (en) Memory buffer arrangement
DE602005016931D1 (de) Tonkanalkonvertierung
TW200738059A (en) Ambience control
ATE353541T1 (de) Sicherheitsschaltgeräte-modulanordnung
TW200504592A (en) Reconfigurable apparatus with high hardware efficiency
DE60331296D1 (de) Implementierung von breiten multiplexern in einer rekonfigurierbaren logischen vorrichtung
DE69023695D1 (de) Initialisierungs-system und -methoden für Eingang/Ausgang-Verarbeitungseinheiten.
ATE499801T1 (de) Optischer kreuzvermittlungsschalter
SE0402098D0 (sv) A control system
ATE507503T1 (de) Vorrichtung zur beeinflussung von licht
DE69531597D1 (de) Testmethode und flipflop mit mutter- und tochtereinheit umfassender elektronischer schaltkreis
DE69607019D1 (de) Gerät zur verwendung als lernspielzeug
WO2005033883A3 (en) Directional pad having integrated acoustic system and lighting system
DE59704879D1 (de) Vorrichtung zum betreiben von zwei funktionsmässig parallelgeschalteten prozessoren
DE60223415D1 (de) Umschaltbarer kombinierer und integrierte kombiniervorrichtung zu seiner verwendung
AU2003292065A1 (en) Method and system for alternatively activating a replaceable hardware unit
DE60329915D1 (de) Datenerfassungssystem
DE60014925D1 (de) Vorrichtung zur signalverarbeitung

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties