ATE523847T1 - Digitaler signalprozessor mit mehreren unabhängigen zugeordneten prozessoren - Google Patents

Digitaler signalprozessor mit mehreren unabhängigen zugeordneten prozessoren

Info

Publication number
ATE523847T1
ATE523847T1 AT00968959T AT00968959T ATE523847T1 AT E523847 T1 ATE523847 T1 AT E523847T1 AT 00968959 T AT00968959 T AT 00968959T AT 00968959 T AT00968959 T AT 00968959T AT E523847 T1 ATE523847 T1 AT E523847T1
Authority
AT
Austria
Prior art keywords
processors
processor
digital signal
signal processor
input
Prior art date
Application number
AT00968959T
Other languages
English (en)
Inventor
David Vavro
James Mitchell
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Application granted granted Critical
Publication of ATE523847T1 publication Critical patent/ATE523847T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G06F9/30014—Arithmetic instructions with variable precision
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7817—Specially adapted for signal processing, e.g. Harvard architectures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30101—Special purpose registers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Signal Processing (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Advance Control (AREA)
  • Multi Processors (AREA)
  • Executing Machine-Instructions (AREA)
  • Image Processing (AREA)
AT00968959T 1999-12-17 2000-10-16 Digitaler signalprozessor mit mehreren unabhängigen zugeordneten prozessoren ATE523847T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/465,634 US7793076B1 (en) 1999-12-17 1999-12-17 Digital signals processor having a plurality of independent dedicated processors
PCT/US2000/028630 WO2001044964A2 (en) 1999-12-17 2000-10-16 Digital signal processor having a plurality of independent dedicated processors

Publications (1)

Publication Number Publication Date
ATE523847T1 true ATE523847T1 (de) 2011-09-15

Family

ID=23848555

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00968959T ATE523847T1 (de) 1999-12-17 2000-10-16 Digitaler signalprozessor mit mehreren unabhängigen zugeordneten prozessoren

Country Status (8)

Country Link
US (2) US7793076B1 (de)
EP (1) EP1238343B1 (de)
JP (1) JP4391053B2 (de)
KR (1) KR100472706B1 (de)
AT (1) ATE523847T1 (de)
AU (1) AU7879800A (de)
TW (1) TW513638B (de)
WO (1) WO2001044964A2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7085285B2 (en) 2000-03-01 2006-08-01 Realtek Semiconductor Corp. xDSL communications systems using shared/multi-function task blocks
JP2002149402A (ja) * 2000-11-14 2002-05-24 Pacific Design Kk データ処理装置およびその制御方法
JP4783527B2 (ja) 2001-01-31 2011-09-28 株式会社ガイア・システム・ソリューション データ処理システム、データ処理装置およびその制御方法
JP4865960B2 (ja) 2001-06-25 2012-02-01 株式会社ガイア・システム・ソリューション データ処理装置およびその制御方法
US6993674B2 (en) 2001-12-27 2006-01-31 Pacific Design, Inc. System LSI architecture and method for controlling the clock of a data processing system through the use of instructions
US7714870B2 (en) * 2003-06-23 2010-05-11 Intel Corporation Apparatus and method for selectable hardware accelerators in a data driven architecture
US8145879B2 (en) * 2005-11-29 2012-03-27 Xmtt Inc. Computer memory architecture for hybrid serial and parallel computing systems
US9702305B2 (en) 2013-04-17 2017-07-11 Micron Technology, Inc. Multiple engine sequencer

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5083204A (en) 1984-10-01 1992-01-21 Hughes Aircraft Company Signal processor for an imaging sensor system
US4745544A (en) * 1985-12-12 1988-05-17 Texas Instruments Incorporated Master/slave sequencing processor with forced I/O
JPS62168260A (ja) 1986-01-20 1987-07-24 Mitsubishi Electric Corp ワンチツプマイクロコンピユ−タ
JPH0337723A (ja) * 1989-07-05 1991-02-19 Hitachi Ltd 情報処理装置
US5197140A (en) * 1989-11-17 1993-03-23 Texas Instruments Incorporated Sliced addressing multi-processor and method of operation
US5440752A (en) 1991-07-08 1995-08-08 Seiko Epson Corporation Microprocessor architecture with a switch network for data transfer between cache, memory port, and IOU
US5397321A (en) * 1993-07-30 1995-03-14 Ep Technologies, Inc. Variable curve electrophysiology catheter
KR100186916B1 (ko) 1994-02-14 1999-05-01 모리시다 요이치 신호처리장치
US5742840A (en) * 1995-08-16 1998-04-21 Microunity Systems Engineering, Inc. General purpose, multiple precision parallel operation, programmable media processor
GB2311882B (en) * 1996-04-04 2000-08-09 Videologic Ltd A data processing management system
JPH11261958A (ja) 1998-03-09 1999-09-24 Sony Corp 映像編集装置及び映像編集方法
JP2000057122A (ja) * 1998-08-06 2000-02-25 Yamaha Corp デジタル信号処理装置

Also Published As

Publication number Publication date
JP2003517684A (ja) 2003-05-27
JP4391053B2 (ja) 2009-12-24
EP1238343A2 (de) 2002-09-11
EP1238343B1 (de) 2011-09-07
KR20020059763A (ko) 2002-07-13
TW513638B (en) 2002-12-11
KR100472706B1 (ko) 2005-03-10
WO2001044964A2 (en) 2001-06-21
AU7879800A (en) 2001-06-25
US20100306502A1 (en) 2010-12-02
WO2001044964A3 (en) 2002-04-25
US8019972B2 (en) 2011-09-13
US7793076B1 (en) 2010-09-07

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