JPS5710870A - Matrix operation system - Google Patents
Matrix operation systemInfo
- Publication number
- JPS5710870A JPS5710870A JP8535380A JP8535380A JPS5710870A JP S5710870 A JPS5710870 A JP S5710870A JP 8535380 A JP8535380 A JP 8535380A JP 8535380 A JP8535380 A JP 8535380A JP S5710870 A JPS5710870 A JP S5710870A
- Authority
- JP
- Japan
- Prior art keywords
- result
- multiplication
- registers
- components
- matrixes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Mathematical Physics (AREA)
- Pure & Applied Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Computational Mathematics (AREA)
- Data Mining & Analysis (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- Algebra (AREA)
- Databases & Information Systems (AREA)
- Software Systems (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Abstract
PURPOSE:To reduce a processing time of a computer when the degree of a matrix increases, by storing the components which have been decided in advance, of two matrixes, in registers, respectively, multiplying in parallel the outputs of the respective corresponding components by one control signal, and adding its result. CONSTITUTION:Two multioperation registers 2, 3 of an operation part 5 are designated, and components which have been decided in advance, of two matrixes are shifted from a memory 4. A multiplying instruction of the respective corresponding components between the registers 2, 3 is outputted from a control part 1, the multiplication is executed in parallel in the operation part 5, and its result is newly set in the register 3. Subsequently, an adding instruction of K times is given to the register 3 which has stored a result of multiplication, and a result of addition is set to a prescribed area of the memory 4. In this way, since the processing is executed by multiplication of once and addition of K times, a processing time of a computer is shortened remarkably.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8535380A JPS5710870A (en) | 1980-06-24 | 1980-06-24 | Matrix operation system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8535380A JPS5710870A (en) | 1980-06-24 | 1980-06-24 | Matrix operation system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5710870A true JPS5710870A (en) | 1982-01-20 |
Family
ID=13856315
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8535380A Pending JPS5710870A (en) | 1980-06-24 | 1980-06-24 | Matrix operation system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5710870A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007029563A (en) * | 2005-07-28 | 2007-02-08 | Eko:Kk | Shaft for golf club |
-
1980
- 1980-06-24 JP JP8535380A patent/JPS5710870A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007029563A (en) * | 2005-07-28 | 2007-02-08 | Eko:Kk | Shaft for golf club |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
KR950033803A (en) | Multiple bit shift device, data processor using same, and multiple bit shift method | |
EP0378415A3 (en) | Multiple instruction dispatch mechanism | |
JPS5779557A (en) | Data processor | |
JPS52119832A (en) | Electroinc calculator of microprogram control system | |
JPS56123069A (en) | Data processing device | |
JPS5710870A (en) | Matrix operation system | |
ES321002A1 (en) | A disposition of numeric circuits by digits to execute arithmetic operations. (Machine-translation by Google Translate, not legally binding) | |
GB1332031A (en) | Information processing systems | |
JPS55108057A (en) | Duplex control unit | |
JPS5595148A (en) | Binary arithmetic circuit | |
JPS5748141A (en) | Address conversion system | |
JPS5789175A (en) | Data processing control system | |
JPS56124954A (en) | Advance control type information processing equipment | |
JPS56159734A (en) | Arithmetic system | |
JPS5578339A (en) | Multiplication system | |
JPS5647846A (en) | Parity check system | |
FR2378313A1 (en) | Microprocessor memory access control system - uses exterior programme counter to process different lengths of instructions | |
JPS6459553A (en) | Address conversion circuit | |
JPS5789173A (en) | Data processing control system | |
JPS57169856A (en) | Instruction execution system | |
JPS5578340A (en) | Division system | |
JPS57132226A (en) | Interprocessor data transfer system | |
JPS5785147A (en) | Microprogram control device | |
GB2010548A (en) | Electronic Calculating Arrangement | |
JPS57161940A (en) | Central processing device |