JP2015521336A5 - - Google Patents

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Publication number
JP2015521336A5
JP2015521336A5 JP2015503674A JP2015503674A JP2015521336A5 JP 2015521336 A5 JP2015521336 A5 JP 2015521336A5 JP 2015503674 A JP2015503674 A JP 2015503674A JP 2015503674 A JP2015503674 A JP 2015503674A JP 2015521336 A5 JP2015521336 A5 JP 2015521336A5
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JP
Japan
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coupled
fram
circuit
line
lines
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JP2015503674A
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English (en)
Japanese (ja)
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JP6247280B2 (ja
JP2015521336A (ja
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Priority claimed from US13/435,718 external-priority patent/US8756558B2/en
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Publication of JP2015521336A5 publication Critical patent/JP2015521336A5/ja
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JP2015503674A 2012-03-30 2013-04-01 強誘電性ランダムアクセスメモリ（ｆｒａｍ）レイアウト装置及び方法 Active JP6247280B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/435,718 2012-03-30
US13/435,718 US8756558B2 (en) 2012-03-30 2012-03-30 FRAM compiler and layout
PCT/US2013/034785 WO2013149235A1 (en) 2012-03-30 2013-04-01 Ferroelectric random access memory (fram) layout apparatus and method

Publications (3)

Publication Number Publication Date
JP2015521336A JP2015521336A (ja) 2015-07-27
JP2015521336A5 true JP2015521336A5 (enExample) 2016-05-26
JP6247280B2 JP6247280B2 (ja) 2017-12-13

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ID=49234833

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015503674A Active JP6247280B2 (ja) 2012-03-30 2013-04-01 強誘電性ランダムアクセスメモリ（ｆｒａｍ）レイアウト装置及び方法

Country Status (4)

Country Link
US (1) US8756558B2 (enExample)
JP (1) JP6247280B2 (enExample)
CN (1) CN104205227B (enExample)
WO (1) WO2013149235A1 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10283181B2 (en) 2016-03-01 2019-05-07 Texas Instruments Incorporated Time tracking circuit for FRAM
US9721639B1 (en) * 2016-06-21 2017-08-01 Micron Technology, Inc. Memory cell imprint avoidance
GB2557994B (en) 2016-12-21 2020-01-15 Subsea 7 Ltd Supporting saturation divers underwater using a UUV with ancillary electrical equipment
US10418085B2 (en) * 2017-07-20 2019-09-17 Micron Technology, Inc. Memory plate segmentation to reduce operating power
US11194947B2 (en) * 2017-09-27 2021-12-07 Intel Corporation Systems and methods for region-based error detection and management in integrated circuits
CN116114019A (zh) * 2020-09-22 2023-05-12 株式会社半导体能源研究所 半导体装置及电子设备
CN117980993A (zh) * 2021-11-30 2024-05-03 华为技术有限公司 铁电存储器、数据读取方法及电子设备
CN116312674B (zh) * 2021-12-21 2025-06-27 长鑫存储技术有限公司 存储阵列自动扩展方法、装置、设备及介质
CN118380038B (zh) * 2024-06-21 2024-09-17 晶铁半导体技术(广东)有限公司 一种铁电存储器纠错方法、系统、设备及产品

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02264451A (ja) * 1989-04-05 1990-10-29 Mitsubishi Electric Corp フロアプラン設計支援装置
KR100297874B1 (ko) * 1997-09-08 2001-10-24 윤종용 강유전체랜덤액세스메모리장치
US6809949B2 (en) 2002-05-06 2004-10-26 Symetrix Corporation Ferroelectric memory
US7073158B2 (en) * 2002-05-17 2006-07-04 Pixel Velocity, Inc. Automated system for designing and developing field programmable gate arrays
KR100448921B1 (ko) 2002-05-21 2004-09-16 삼성전자주식회사 고속 강유전체 메모리 장치 및 그것의 기입 방법
KR100492799B1 (ko) * 2002-11-08 2005-06-07 주식회사 하이닉스반도체 강유전체 메모리 장치
KR100499631B1 (ko) * 2002-11-08 2005-07-05 주식회사 하이닉스반도체 강유전체 메모리 장치
US7461371B2 (en) 2003-09-11 2008-12-02 Taiwan Semiconductor Manufacturing Company, Ltd. General purpose memory compiler system and associated methods
US6930934B2 (en) 2003-10-28 2005-08-16 Taiwan Semiconductor Manufacturing Co., Ltd. High efficiency redundancy architecture in SRAM compiler
KR100835468B1 (ko) 2006-07-27 2008-06-04 주식회사 하이닉스반도체 불휘발성 강유전체 메모리 장치 및 그 리프레쉬 방법
WO2008029439A1 (fr) * 2006-09-04 2008-03-13 Renesas Technology Corp. Dispositif informatique de support à la conception et compilateur de mémoire
US7561458B2 (en) 2006-12-26 2009-07-14 Texas Instruments Incorporated Ferroelectric memory array for implementing a zero cancellation scheme to reduce plateline voltage in ferroelectric memory
US8154938B2 (en) 2009-03-06 2012-04-10 Texas Instruments Incorporated Memory array power domain partitioning
US8081500B2 (en) 2009-03-31 2011-12-20 Ramtron International Corporation Method for mitigating imprint in a ferroelectric memory

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