Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F30/00—Computer-aided design [CAD]
  • G06F30/30—Circuit design
  • G06F30/39—Circuit design at the physical level

Definitions

• FRAM ferroelectric random access memory
• SRAM static random access memory
• DRAM dynamic random access memory
• a user is able to input design criteria for a memory (i.e., DRAM or SRAM array), and a computer system or personal computer (PC) that can automatically generate a layout for such a memory, which significantly reduces overhead in designing integrated circuits (ICs) that include SRAM or DRAM.
• FRAMs on the other hand, that have not been designed using compilers due to complexities in design that are not generally amiable to use in compilers; as a result, FRAMs have traditionally been the focus of custom designs, which is time consuming and labor intensive. Therefore, there is a need for an FRAM compiler.
• Patent No. 7,461,371 U.S. Patent Pre-Grant Publ. No. 2005/0088887; and U.S. Patent Pre-Grant Publ. No. 2010/0226162.
• An aspect of the invention provides an apparatus.
• the apparatus comprises a first array segment having: an first array of ferroelectric memory cells arranged into a first set of rows and a first set of columns, wherein each row from the first set of rows is associated with at least one bitline from a first set of bitlines and at least one plateline from a first set of platelines, and wherein each column from the first set of columns is associated with at least one wordline from a first set of wordlines; and a first set of bitline cells, wherein each bitline is coupled to at least one bitline from the first set of bitlines; a second array segment having: an second array of ferroelectric memory cells arranged into a second set of rows and a second set of columns, wherein each row from the second set of rows is associated with at least one bitline from a second set of bitlines and at least one plateline from a second set of platelines, and wherein each column from the second set of columns is associated with at least one wordline from a second set of wordlines; and a second set of bit
• each bitline cell may comprise a precharge circuit.
• Each bitline cell may be coupled to a pair of bitlines, wherein each bitline cell further comprises: the precharge circuit being coupled to its pair of bitlines, and a multiplexer that is coupled to the precharge circuit and its sense amplifier wherein the multiplexer is controlled by the controller.
• each bitline from the first and second sets of bitlines may comprise a true bitline and a complement bitline
• each ferroelectric memory cell may comprise: a first MOS transistor that is coupled to its true bitline at its drain and its wordline at its gate; a first ferroelectric capacitor that is coupled between the source of the first MOS transistor and its plateline; a second MOS transistor that is coupled to its complement bitline at its drain and its wordline at its gate; and a second ferroelectric capacitor that is coupled between the source of the second MOS transistor and its plateline.
• the ECC logic circuit may further comprise: a plurality of syndrome generators that are coupled to receive an uncorrected read from the sensing circuit; a plurality of error corrector circuits; and a plurality of error corrector parity circuits, wherein the plurality of error corrector circuits and the plurality of error corrector parity circuits are coupled to the plurality of syndrome generators so as to generate a corrected read.
• the first row interface circuit may be adjacent to the first array segment, and the second row interface circuit may be adjacent to the second array segment.
• Another aspect of the invention provides a computer program for generating a layout for a ferroelectric random access memory (FRAM) that is embodied on a non-transitory storage medium and executable by a processor is provided.
• FRAM ferroelectric random access memory
• the computer program comprises computer code for receiving FRAM specifications, computer code for retrieving an FRAM floorplan and design rules from the non-transitory storage medium, and computer code for assembling the layout for the FRAM based on the FRAM specifications and design rules.
• the FRAM specifications may further comprise a word size, a bit length, byte size, and array segment layout.
• the design rules may further comprise: computer code for placing row interface circuitry along one edge of the layout; and computer code for placing a controller at one corner of the layout, wherein the controller is substantially adjacent to the row interface circuitry.
• the floorplan may further comprise a shared circuit and a scalable circuit.
• a FRAM having a layout is provided.
• the FRAM comprises a shared circuit having row interface circuitry located along an edge of the layout; and a controller that is coupled to the row interface circuitry, that is substantially adjacent to the row interface circuitry, and that is located at a corner of the layout; and a plurality of scalable circuits that are arranged in a array, wherein the array is adjacent to the row interface circuitry, wherein each scalable circuit includes: a first set of bitlines; a second set of bitlines; a first set of wordlines, wherein each wordline from the first set of wordlines is coupled to the row interface circuitry; a second set of wordlines, wherein each wordline from the second set of wordlines is coupled to the row interface circuitry; a first set of plate lines; a second set of platelines; a first set of FRAM cells arranged into a first set of rows and a first set of columns, wherein each FRAM cell from the first set of FRAM cells is coupled to at least one bitline from the first set of bitlines, at least
• the first set of bitlines may further comprise a first set of true bitlines and a first set of complement bitlines
• the second set of bitlines further comprises a second set of true bitlines and a second set of complement bitlines.
• Each FRAM cell from the first and second sets of FRAM cells may further comprise: a first NMOS transistor that is coupled to its true bitline at its drain and its wordline at its gate; a first ferroelectric capacitor that is coupled between the source of the first MOS transistor and its plateline; a second NMOS transistor that is coupled to its complement bitline at its drain and its wordline at its gate; and a second ferroelectric capacitor that is coupled between the source of the second MOS transistor and its plateline.
• Each bitline cell from the first and second sets of bitline cells may further comprise: a precharge circuit that is coupled to true and complement bitlines from two adjacent rows in its associated set of FRAM cells; and a multiplexer that is coupled to the precharge circuit and its sense amplifier, wherein the multiplexer is controlled by the controller.
• the row interface circuitry may further comprise: a first row driver that is coupled to each first set of FRAM cells in a row of the array; a first row decoder that is coupled to the first row driver; a second row driver that is coupled to each second set of FRAM cells in the row of the array; and a second row decoder that is coupled to the second row driver; and a wordline boost circuit that is coupled to the first and second row drivers and that is located between the first and second row drivers.
• the ECC logic circuit may further comprise: a plurality of syndrome generators that are coupled to receive an uncorrected read from its sensing circuit; a plurality of error corrector circuits; and a plurality of error corrector parity circuits, wherein the plurality of error corrector circuits and the plurality of error corrector parity circuits are coupled to the plurality of syndrome generators so as to generate a corrected read.
• Each of the first and second row drivers may further comprise a row shifting circuit.
• the bit length for the FRAM may be 64 bits, he array is one of a 1x2 array of scalable circuits, a 1x4 array of scalable circuits, a 2x2 array of scalable circuits, a 1x8 array of scalable circuits, a 2x4 array of scalable circuits, a 4x2 array of scalable circuits, a 2x8 array of scalable circuits, a 4x4 array of scalable circuits, and a 4x8 array of scalable circuits having respective word sizes of 1024, 2048, 2048, 4096, 4096, 4096, 8192, 8192, and 16384 and having a respective size of 8kb, 16kb, 16kb, 32kb, 32kb, 32kb, 64kb, 64kb, 128kb.
• FIG. 1 is a diagram of an example of a computer system.
• FIG. 2 is a diagram of an example of an FRAM compiler in accordance with the present invention, which can be used on the computer system of FIG. 1.
• FIG. 3 is a diagram of an example of an FRAM floorplan
• FIG. 4 is a diagram of an example of an FRAM cell of FIG. 3.
• FIG. 5 is a diagram of an example of a bitline cell of FIG. 3.
• FIG. 6 is a diagram of an example of a sense amplifier of FIG. 3.
• FIG. 7 is a diagram of an example of a row shift for the array segments of FIG. 3
• FIG. 8 is a diagram of an example of a row shift circuit employed in the row drivers of FIG. 3.
• FIG. 9 is a diagram of an example of a column shift for the array segments of
• FIG. 10 is a diagram of an example of the error correcting code (ECC) logic circuit of FIG. 3.
• ECC error correcting code
• FIGS. 11-14 are diagrams of examples of FRAM memory circuits generated by the compiler of FIG. 2 using the floorplan of FIG. 3.
• Network 100 generally comprises personal computers (PCs) or terminals 102-1 to 102-N, a packet switching network 104, and a large scale computation computer 106.
• PCs personal computers
• terminals 102-1 to 102-N include one or more processors and a storage medium (such as random access memories and hard disk drives), where the processor can execute computer program code or software instructions which are stored in the storage media.
• Circuit compilers (which are generally computer code or software instructions) generally take many forms and which can operate or be executed on one or more of the PCs 102-1 to 102-N or over the network 104.
• FIG. 2 illustrates a generalized diagram of a FRAM compiler 204.
• Compiler 204 generally operates over one or more computers 102-1 to 102-N and 106 on computer network 100 so as to generate a layout for a FRAM memory circuit.
• a user is able to define FRAM specifications (such as word size, bit length, total size, and layout aspect ratio).
• the engine 206 is able to retrieve an FRAM floorplan 210 retrieved from a storage medium 208 (such as a hard disk drive), and, based on the FRAM specifications 202 and design rules 212, the engine 206 is able to form an FRAM memory (generally for use in an integrated circuit or IC) as the results 218.
• the floorplan 210 (an example of which can be seen in FIG. 3) can set forth the general arrangement for an FRAM memory. As shown in the example of FIG. 3, the floorplan 210 has two components: the shared circuit 301 and the scalable circuit 303.
• the shared circuit 301 is generally formed of circuits that can be shared across scalable circuit 303 (and which can, in part, be described by design rules 212), while the scalable circuit 303 can be expanded to achieve the desired size, aspect ratio, and so forth.
• FIG. 3 the shared circuit 301
• the shared circuit 301 is generally formed of circuits that can be shared across scalable circuit 303 (and which can, in part, be described by design rules 212), while the scalable circuit 303 can be expanded to achieve the desired size, aspect ratio, and so forth.
• the shared circuit 301 is located along one edge with a controller 322 at one corner and row interface circuitry (i.e., row interface circuits for the upper and lower array segments 310-1 and 310-2 and wordline boost circuit 316) being substantially adjacent to the controller 322.
• row interface circuitry i.e., row interface circuits for the upper and lower array segments 310-1 and 310-2 and wordline boost circuit 316
• Each row decoder 302-1 and 302- 2 and row driver 304-1 and 304-1 can be used to driver row for any number of array segments (i.e., 310-1 and 310-2) expanded horizontally.
• the scalable circuit 303 can, for example, be generally formed of pairs of array segments 310-1 and 310-2 (which are generally cell arrays 311-1 and 311-2 and bitline circuits 312-1 and 312-2) that share (and are substantially adjacent to) a sensing circuit 314 (which, for example, includes sense amplifiers 328) and that share an input/output (IO) bus 318 and an ECC logic circuit 320.
• the cell arrays 311-1 and 311-2 (which can, for example, be 32 bits wide) also generally include FRAM cells 324 arranged into an array of rows and columns, and bitline circuits 312-1 and 312- 2 and generally include bitline cells 326.
• FRAM cell 324 An example of FRAM cell 324 is illustrated in FIG. 4. As shown, the FRAM cell
• transistors Ql and Q2 are NMOS transistors that are coupled to true and complement bitlines BL and BL , respectively.
• Transistors Ql and Q2 also share a plateline PL that is generally coupled to its plate line driver (i.e., 308-1 or 308-2) and share a wordline WL that is generally coupled to its row driver (i.e., 304-1 or 304-2). These transistors Ql and Q2 can then be used to control or assist in reading the state of ferroelectric capacitors CI and C2 or in the writing of a state to ferroelectric capacitors CI and C2.
• bitline circuits i.e., 312-1 and 312-2
• bitline cells 326 may be shared by multiple sets of true and complement bitlines BL and BL , although it is possible to employ one bitline cell 326 for each set of true and complement bitlines BL and BL .
• bitline cell 324 generally comprises a precharge circuit 402 (which generally comprises transistors Q3 to Q8), a restoration circuit 404 (which generally comprises transistors Q9 to Q20), and a multiplexer or mux 406 (which generally comprises transistors Q21 to Q24).
• the precharge circuit 402 is generally controlled by controller 322 using the precharge signal PRE and is coupled to rail VDD so as to be able to precharge the bitlines BL1, BL2, BL ⁇ , and BL2 .
• the restoration circuit 404 (which can generally provide some test functionality) is generally controlled by controller 322 with control signal CNTL and is coupled to rail VSS.
• the mux 406 is controlled by controller 322 with select signal SELECT, where the mux 406 can output states from true and complement bitlines BL1 and BL ⁇ or true and complement bitlines BL2 andBL2 on output bitlines BLO and BLO .
• sense amplifiers 328 are coupled to a bitline cell 324 from each of a pair of bitline circuits 312-1 and 312-2, as shown in the example of FIG. 6.
• the sense amplifier 328 is generally comprised of transistors Q25 to Q28, and the sense amplifier 328 is usually enabled and disabled based on the sense enable signal SE (and its complement or inverse signal SE ) that is provided by controller 322.
• the sense amplifier 328 is also able to perform portions of read and write operations based on the state of the read/write signal RW (which is also generally provided by controller 322), and the bitlines BLO and BLO are able to be coupled together based on the state of signal PRC (which is also generally provided by controller).
• FIGS. 3 and 7-9 To increase the manufacturability and reliability, several other features (which can, for example, be seen in FIGS. 3 and 7-9) can be added to the cell arrays (i.e., 311-1 and 311- 1). Usually, a strip of dummy FRAM cells (i.e., 324) can be included on the periphery of the cell array (i.e., 311-1 or 311-2) to reduce the effects of process gradients across the arrays (i.e., 311-1 or 311-2).
• the array i.e., 311-1 and 311-2
• the array i.e., 311-1 and 311-2
• the row decoders i.e., 304-1 and 304-2
• a row shift circuit 400 (a portion of an example of which can be seen in FIG. 8).
• NAND gate 502 and inverter 504 generally operate as a shift control circuit (with signal REDZ being an active low signal indicating a shift) by generating signals SHIFT and SHIFTZ.
• the signals SHIFT and SHITFZ are complementary or inverses of one another and are used to activate or deactivate drivers 506 and 508. For example, when signal REDZ is low or "0,” driver 508 is deactivated, while driver 506 is activated.
• signals SHIFTZ and REDZ can be used to control transistors Q34 and Q35 (which as shown are PMOS transistors) so as to be able to couple the output of driver (i.e., faulty wordline) to rail VDD.
• a similar circuit may also be provided for column shifting.
• ECC logic circuit 320 is generally comprised of syndrome generators 602-1 to 602-8, error corrector circuits 604-1 to 604-3, and error corrector parity circuits 606-1 to 606-3. For example, with a 64 bit word, 8 parity bits can be added, and a 64 bit, uncorrected read can be provided to syndrome generators 602-1 to 602-8.
• error corrector circuit 604- 1 can perform error correction for first bit or least significant bit of the 64 bit word, and the error corrector circuits 604-2 and 604-3 perform error correction for the following 62 bits and the most significant bit (respectively). Additionally, for this example, error corrector parity circuits 606-1 to 606-3 perform error correction for first bit or least significant bit of the 8 parity bits, the following 6 bits, and the most significant bit of the 8 parity bits.
• ECC logic circuit 320 can produce a 64 bit corrected read for this example.
• 7 parity bits can be added, and a 32 bit, uncorrected read can be provided to syndrome generators 602-1 to 602-8 (with unused inputs being coupled to rail VSS).
• error corrector circuit 604-1 can perform error correction for first bit or least significant bit of the 32 bit word, and the error corrector circuits 604-2 and 604-3 perform error correction for the following 30 bits and the most significant bit (respectively). Additionally, for this example, error corrector parity circuits 606-1 to 606-3 perform error correction for first bit or least significant bit of the 7 parity bits, the following 5 bits, and the most significant bit of the 7 parity bits.
• ECC logic circuit 320 can produce a 32 bit corrected read for this example.
• FIGS. 11-14 show examples of FRAM memory circuits 700-A to 700-D.
• FRAM memory circuits 700-A to 700-D can be generated by compiler 206 using the floorplan 210 (for use in an IC, for example).
• the minimum size scalable circuit 303 i.e., lxl aspect ratio
• the minimum size scalable circuit 303 includes two array segments (which are labeled 310 for the sake of simplicity of illustration).
• row decoder, row driver, plate driver, and sensing circuit are respectively labeled 304, 304, 308 and 314 for the sake of simplicity of illustration.
• FRAM memory circuits 700-A to 700-D have aspect ratios of 1x2, 1x4, 4x1, and 4x4, respectively, that result in different memory sizes
• the design rules 212 can include adaptations to the controller 322 (which can include timing, clocking, and IO circuitry) to accommodate these different sizes (i.e., up to, for example, 1Mb) of FRAM memory circuits (i.e., 700-D), which can be specified by FRAM specifications. Examples of FRAM specifications (i.e., 202) can also be found in Table 1 below.

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