JP2018064059A - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP2018064059A
JP2018064059A JP2016202787A JP2016202787A JP2018064059A JP 2018064059 A JP2018064059 A JP 2018064059A JP 2016202787 A JP2016202787 A JP 2016202787A JP 2016202787 A JP2016202787 A JP 2016202787A JP 2018064059 A JP2018064059 A JP 2018064059A
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JP
Japan
Prior art keywords
film
interlayer insulating
disposed
insulating film
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2016202787A
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English (en)
Japanese (ja)
Other versions
JP2018064059A5 (https=
Inventor
洋一 芦田
Yoichi Ashida
洋一 芦田
藤原　剛
Takeshi Fujiwara
剛 藤原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Original Assignee
Denso Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denso Corp filed Critical Denso Corp
Priority to JP2016202787A priority Critical patent/JP2018064059A/ja
Priority to PCT/JP2017/030227 priority patent/WO2018070111A1/ja
Publication of JP2018064059A publication Critical patent/JP2018064059A/ja
Publication of JP2018064059A5 publication Critical patent/JP2018064059A5/ja
Priority to US16/355,917 priority patent/US10916506B2/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/497—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
JP2016202787A 2016-10-14 2016-10-14 半導体装置 Pending JP2018064059A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2016202787A JP2018064059A (ja) 2016-10-14 2016-10-14 半導体装置
PCT/JP2017/030227 WO2018070111A1 (ja) 2016-10-14 2017-08-24 半導体装置
US16/355,917 US10916506B2 (en) 2016-10-14 2019-03-18 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2016202787A JP2018064059A (ja) 2016-10-14 2016-10-14 半導体装置

Publications (2)

Publication Number Publication Date
JP2018064059A true JP2018064059A (ja) 2018-04-19
JP2018064059A5 JP2018064059A5 (https=) 2019-01-17

Family

ID=61906230

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016202787A Pending JP2018064059A (ja) 2016-10-14 2016-10-14 半導体装置

Country Status (3)

Country Link
US (1) US10916506B2 (https=)
JP (1) JP2018064059A (https=)
WO (1) WO2018070111A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR102932512B1 (ko) * 2020-04-29 2026-03-03 삼성전자주식회사 배선 구조체 및 이를 포함하는 반도체 패키지
CN111900087B (zh) * 2020-08-31 2022-09-20 华虹半导体(无锡)有限公司 Igbt器件的制造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008091454A (ja) * 2006-09-29 2008-04-17 Rohm Co Ltd 半導体装置及び半導体装置の製造方法
JP2008147786A (ja) * 2006-12-06 2008-06-26 Denso Corp 絶縁ゲートトランジスタの駆動回路
JP2011216771A (ja) * 2010-04-01 2011-10-27 Rohm Co Ltd 半導体装置およびその製造方法
JP2016115892A (ja) * 2014-12-17 2016-06-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0766201A (ja) * 1993-08-27 1995-03-10 Matsushita Electric Ind Co Ltd 配線のエレクトロマイグレーション寿命試験用半導体装置及びその製造方法、並びにその試験方法
JPH1154621A (ja) * 1997-08-07 1999-02-26 Sony Corp 半導体装置およびその製造方法
JP4051524B2 (ja) * 2000-09-18 2008-02-27 セイコーエプソン株式会社 インパクトプリンタのヘッド駆動回路
US6733195B2 (en) 1999-10-22 2004-05-11 Seiko Epson Corporation Head drive circuit for impact dot printer
EP1093925B1 (en) * 1999-10-22 2006-02-15 Seiko Epson Corporation Head drive circuit for impact dot printer
JP4528035B2 (ja) * 2004-06-18 2010-08-18 ルネサスエレクトロニクス株式会社 半導体装置
JP2008244383A (ja) * 2007-03-29 2008-10-09 Casio Comput Co Ltd 半導体装置およびその製造方法
US7772080B2 (en) * 2008-07-02 2010-08-10 Stats Chippac, Ltd. Semiconductor device and method of providing electrostatic discharge protection for integrated passive devices
JP2012094593A (ja) * 2010-10-25 2012-05-17 Renesas Electronics Corp 半導体装置および半導体装置の製造方法
JP5772926B2 (ja) * 2013-01-07 2015-09-02 株式会社デンソー 半導体装置
JP6235353B2 (ja) * 2014-01-22 2017-11-22 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008091454A (ja) * 2006-09-29 2008-04-17 Rohm Co Ltd 半導体装置及び半導体装置の製造方法
JP2008147786A (ja) * 2006-12-06 2008-06-26 Denso Corp 絶縁ゲートトランジスタの駆動回路
JP2011216771A (ja) * 2010-04-01 2011-10-27 Rohm Co Ltd 半導体装置およびその製造方法
JP2016115892A (ja) * 2014-12-17 2016-06-23 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法

Also Published As

Publication number Publication date
US10916506B2 (en) 2021-02-09
WO2018070111A1 (ja) 2018-04-19
US20190214346A1 (en) 2019-07-11

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