JP2018046234A - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP2018046234A JP2018046234A JP2016181589A JP2016181589A JP2018046234A JP 2018046234 A JP2018046234 A JP 2018046234A JP 2016181589 A JP2016181589 A JP 2016181589A JP 2016181589 A JP2016181589 A JP 2016181589A JP 2018046234 A JP2018046234 A JP 2018046234A
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
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Abstract
【解決手段】半導体基板SB上に絶縁層BXと半導体層SMと絶縁膜ZM1とが積層され、溝TRに素子分離領域STが埋め込まれた基板を準備する。バルク領域1Bの絶縁膜ZM1をドライエッチングにより除去してから、バルク領域1Bの半導体層SMをドライエッチングにより除去した後、バルク領域1Bの絶縁層BXをドライエッチングにより薄くする。SOI領域1Aの半導体基板SBにイオン注入により第1半導体領域を形成し、バルク領域1Bの半導体基板SBにイオン注入により第2半導体領域を形成する。その後、SOI領域1Aの絶縁膜ZM1とバルク領域1Bの絶縁層BXとをウェットエッチングにより除去する。その後、SOI領域1Aの半導体層SMに第1トランジスタを形成し、バルク領域1Bの半導体基板SBに第2トランジスタを形成する。
【選択図】図9
Description
<半導体装置の製造工程について>
本実施の形態の半導体装置の製造工程を図面を参照して説明する。図1および図2は、本発明の一実施の形態である半導体装置の製造工程を示すプロセスフロー図である。図3〜図37は、本発明の一実施の形態である半導体装置の製造工程中の要部断面図または要部平面図である。なお、図3〜図37のうち、図3〜図23および図26〜図37は要部断面図であり、図24および図25は要部平面図である。
本発明者が検討した検討例について、図38〜図45を参照して説明する。図38は検討例の半導体装置の製造工程を示すプロセスフロー図であり、上記図2に相当するものである。図39〜図45は、検討例の半導体装置の製造工程中の要部断面図である。
本実施の形態の主要な特徴のうちの一つは、ステップS9,S10,S11の各エッチング工程を、ドライエッチングにより行うことである。本実施の形態の主要な特徴のうちの他の一つは、ステップS11のエッチング工程を行うことである。
1A SOI領域
1B バルク領域
1C 基板
BX 絶縁層
CP1,CP2 キャップ絶縁膜
CPZ 絶縁膜
DT ディボット
EP 半導体層
EX1,EX2 n−型半導体領域
GE1,GE2 ゲート電極
GF1,GF2 ゲート絶縁膜
GP 半導体領域
IL1,IL2 絶縁膜
LM,LM1 積層膜
LT1,LT2 積層体
M1 配線
P1,P2 イオン注入
PG プラグ
PS シリコン膜
PR1,PR2,PR3,PR4,PR5,PR101 フォトレジストパターン
PW p型ウエル
SB 半導体基板
SD1,SD2 n+型半導体領域
SL 金属シリサイド層
SM,SM1 半導体層
ST 素子分離領域
SW1,SW2,SW3 サイドウォールスペーサ
SZ1,SZ2 絶縁膜
TR 溝
ZM1,ZM2,ZM3 絶縁膜
Claims (18)
- (a)半導体基板と、前記半導体基板上の絶縁層と、前記絶縁層上の半導体層と、前記半導体層上の第1絶縁膜と、前記第1絶縁膜、前記半導体層および前記絶縁層を貫通して前記半導体基板に達する溝と、前記溝内に埋め込まれた素子分離領域と、を有する基板を準備する工程、
ここで、前記絶縁層と前記第1絶縁膜と前記素子分離領域とは同じ材料からなり、
(b)前記(a)工程後、前記基板の第1領域の前記第1絶縁膜を覆いかつ前記基板の前記第1領域とは異なる第2領域の前記第1絶縁膜を露出する第1マスク層を形成する工程、
(c)前記(b)工程後、前記第1マスク層をエッチングマスクとして用いて、前記第2領域の前記第1絶縁膜をドライエッチングにより除去して前記第2領域の前記半導体層を露出させる工程、
(d)前記(c)工程後、前記第1マスク層をエッチングマスクとして用いて、前記第2領域の前記半導体層をドライエッチングにより除去して前記第2領域の前記絶縁層を露出させる工程、
(e)前記(d)工程後、前記第1マスク層をエッチングマスクとして用いて、前記第2領域の前記絶縁層をドライエッチングして、前記第2領域の前記絶縁層の厚さを薄くする工程、
(f)前記(e)工程後、前記第1マスク層を除去する工程、
(g)前記(f)工程後、前記第1領域の前記半導体基板に不純物をイオン注入して第1半導体領域を形成し、前記第2領域の前記半導体基板に不純物をイオン注入して第2半導体領域を形成する工程、
(h)前記(g)工程後、前記第1領域の前記第1絶縁膜と前記第2領域の前記絶縁層とをウェットエッチングにより除去して、前記第1領域の前記半導体層と前記第2領域の前記半導体基板とを露出させる工程、
(i)前記(h)工程後、前記第1領域の前記半導体層に第1トランジスタを形成し、前記第2領域の前記半導体基板に第2トランジスタを形成する工程、
を有する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(c)工程と前記(d)工程とでは、使用するエッチングガスが相違し、
前記(d)工程と前記(e)工程とでは、使用するエッチングガスが相違している、半導体装置の製造方法。 - 請求項2記載の半導体装置の製造方法において、
前記(c)工程では、前記第1絶縁膜に比べて前記半導体層がエッチングされにくい条件で、前記第2領域の前記第1絶縁膜をドライエッチングにより除去して前記第2領域の前記半導体層を露出させ、
前記(d)工程では、前記半導体層に比べて前記絶縁層がエッチングされにくい条件で、前記第2領域の前記半導体層をドライエッチングにより除去して前記第2領域の前記絶縁層を露出させ、
前記(d)工程のエッチング条件を用いた場合の前記絶縁層のエッチング速度よりも、前記(e)工程のエッチング条件を用いた場合の前記絶縁層のエッチング速度が大きい、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(c)工程および前記(e)工程では、それぞれ、異方性のドライエッチングが行われ、
前記(d)工程では、等方性のドライエッチングが行われる、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(c)工程における前記第1絶縁膜のエッチング速度よりも、前記(e)工程における前記絶縁層のエッチング速度が小さい、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第1絶縁膜と前記絶縁層と前記素子分離領域とは、酸化シリコンからなる、半導体装置の製造方法。 - 請求項6記載の半導体装置の製造方法において、
前記半導体層は、シリコンからなる、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
平面視において、前記第1領域と前記第2領域との境界には、前記素子分離領域が配置されている、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(a)工程で準備された前記基板において、前記第1絶縁膜は前記絶縁層よりも薄い、半導体装置の製造方法。 - 請求項9記載の半導体装置の製造方法において、
前記(e)工程では、前記第2領域の前記絶縁層の厚さが前記第1領域の前記第1絶縁膜の厚さと同じになるように、前記第2領域の前記絶縁層をドライエッチングして前記第2領域の前記絶縁層の厚さを薄くする、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(a)工程は、
(a1)前記半導体基板と、前記半導体基板上の前記絶縁層と、前記絶縁層上の前記半導体層と、前記半導体層上の前記第1絶縁膜と、前記第1絶縁膜上の第2絶縁膜とを有する前記基板を準備する工程、
(a2)前記(a1)工程後、前記第2絶縁膜、前記第1絶縁膜、前記半導体層および前記絶縁層を貫通して前記半導体基板に達する前記溝を形成する工程、
(a3)前記(a2)工程後、前記第2絶縁膜上に、前記溝内を埋めるように、第3絶縁膜を形成する工程、
(a4)前記(a3)工程後、前記溝の外部の前記第3絶縁膜を除去し、前記溝内に、前記第3絶縁膜からなる前記素子分離領域を形成する工程、
(a5)前記(a4)工程後、前記第2絶縁膜をエッチングにより除去する工程、
を有し、
前記第2絶縁膜は、前記第1絶縁膜とは異なる材料からなる、半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において、
前記絶縁層と前記第1絶縁膜と前記第3絶縁膜は、酸化シリコンからなり、
前記第2絶縁膜は、窒化シリコンからなり、
前記(a4)工程では、前記第3絶縁膜を研磨することにより、前記溝の外部の前記第3絶縁膜を除去し、前記溝内に前記第3絶縁膜からなる前記素子分離領域を形成する、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記第1半導体領域は、前記第1トランジスタのしきい値電圧を制御するために形成される、半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、
前記(g)工程では、平面視において前記第1領域の前記半導体層に隣接する領域の前記素子分離領域にも、前記不純物が注入される、半導体装置の製造方法。 - 請求項1記載の半導体装置の製造方法において、
前記(e)工程を終了した段階での前記第2領域の前記絶縁層の厚さは、3nm以上である、半導体装置の製造方法。 - 請求項15記載の半導体装置の製造方法において、
前記(e)工程における前記第2領域の前記絶縁層のエッチング厚みは、3nm以上である、半導体装置の製造方法。 - (a)半導体基板と、前記半導体基板上の絶縁層と、前記絶縁層上の半導体層と、前記半導体層上の第1絶縁膜と、前記第1絶縁膜、前記半導体層および前記絶縁層を貫通して前記半導体基板に達する溝と、前記溝内に埋め込まれた素子分離領域と、を有する基板を準備する工程、
ここで、前記絶縁層と前記第1絶縁膜と前記素子分離領域とは、酸化シリコンからなり、
(b)前記(a)工程後、前記基板の第1領域の前記第1絶縁膜を覆いかつ前記基板の前記第1領域とは異なる第2領域の前記第1絶縁膜を露出する第1マスク層を形成する工程、
(c)前記(b)工程後、前記第1マスク層をエッチングマスクとして用いて、前記第1絶縁膜に比べて前記半導体層がエッチングされにくい条件で、前記第2領域の前記第1絶縁膜をドライエッチングにより除去して前記第2領域の前記半導体層を露出させる工程、
(d)前記(c)工程後、前記第1マスク層をエッチングマスクとして用いて、前記半導体層に比べて前記絶縁層がエッチングされにくい条件で、前記第2領域の前記半導体層をドライエッチングにより除去して前記第2領域の前記絶縁層を露出させる工程、
(e)前記(d)工程後、前記第1マスク層をエッチングマスクとして用いて、前記第2領域の前記絶縁層をドライエッチングして、前記第2領域の前記絶縁層の厚さを薄くする工程、
(f)前記(e)工程後、前記第1マスク層を除去する工程、
(g)前記(f)工程後、前記第1領域の前記半導体基板に不純物をイオン注入して第1半導体領域を形成し、前記第2領域の前記半導体基板に不純物をイオン注入して第2半導体領域を形成する工程、
(h)前記(g)工程後、前記第1領域の前記第1絶縁膜と前記第2領域の前記絶縁層とをウェットエッチングにより除去して、前記第1領域の前記半導体層と前記第2領域の前記半導体基板とを露出させる工程、
(i)前記(h)工程後、前記第1領域の前記半導体層に第1トランジスタを形成し、前記第2領域の前記半導体基板に第2トランジスタを形成する工程、
を有し、
前記(c)工程と前記(d)工程とでは、使用するエッチングガスが相違し、
前記(d)工程と前記(e)工程とでは、使用するエッチングガスが相違し、
前記(d)工程のエッチング条件を用いた場合の前記絶縁層のエッチング速度よりも、前記(e)工程のエッチング条件を用いた場合の前記絶縁層のエッチング速度が大きい、半導体装置の製造方法。 - 請求項17記載の半導体装置の製造方法において、
前記(a)工程で準備された前記基板において、前記絶縁層は前記第1絶縁膜よりも厚く、
前記(e)工程では、前記第2領域の前記絶縁層の厚さが前記第1領域の前記第1絶縁膜の厚さと同じになるように、前記第2領域の前記絶縁層をドライエッチングして前記第2領域の前記絶縁層の厚さを薄くする、半導体装置の製造方法。
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