JP2018010931A5 - - Google Patents
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- Publication number
- JP2018010931A5 JP2018010931A5 JP2016137740A JP2016137740A JP2018010931A5 JP 2018010931 A5 JP2018010931 A5 JP 2018010931A5 JP 2016137740 A JP2016137740 A JP 2016137740A JP 2016137740 A JP2016137740 A JP 2016137740A JP 2018010931 A5 JP2018010931 A5 JP 2018010931A5
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- wiring board
- wiring
- support
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010410 layer Substances 0.000 claims 17
- 238000004519 manufacturing process Methods 0.000 claims 3
- 238000007747 plating Methods 0.000 claims 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims 2
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 claims 2
- 239000012790 adhesive layer Substances 0.000 claims 2
- 229910052802 copper Inorganic materials 0.000 claims 2
- 239000010949 copper Substances 0.000 claims 2
- 229910000365 copper sulfate Inorganic materials 0.000 claims 1
- ARUVKPQLZAKDPS-UHFFFAOYSA-L copper(II) sulfate Chemical compound [Cu+2].[O-][S+2]([O-])([O-])[O-] ARUVKPQLZAKDPS-UHFFFAOYSA-L 0.000 claims 1
- 238000009713 electroplating Methods 0.000 claims 1
- 238000000034 method Methods 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016137740A JP6689691B2 (ja) | 2016-07-12 | 2016-07-12 | 配線基板及びその製造方法 |
| US15/645,017 US10170405B2 (en) | 2016-07-12 | 2017-07-10 | Wiring substrate and semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2016137740A JP6689691B2 (ja) | 2016-07-12 | 2016-07-12 | 配線基板及びその製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2018010931A JP2018010931A (ja) | 2018-01-18 |
| JP2018010931A5 true JP2018010931A5 (enExample) | 2019-04-04 |
| JP6689691B2 JP6689691B2 (ja) | 2020-04-28 |
Family
ID=60940698
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016137740A Active JP6689691B2 (ja) | 2016-07-12 | 2016-07-12 | 配線基板及びその製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US10170405B2 (enExample) |
| JP (1) | JP6689691B2 (enExample) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE112019005745T5 (de) * | 2018-11-15 | 2021-07-29 | Rohm Co., Ltd. | Halbleiterbauelement |
| KR102698875B1 (ko) | 2018-12-13 | 2024-08-27 | 엘지이노텍 주식회사 | 인쇄회로기판 |
| KR20210154450A (ko) * | 2020-06-12 | 2021-12-21 | 엘지이노텍 주식회사 | 인쇄회로기판 및 이의 제조 방법 |
Family Cites Families (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4811081A (en) * | 1987-03-23 | 1989-03-07 | Motorola, Inc. | Semiconductor die bonding with conductive adhesive |
| JP2641869B2 (ja) * | 1987-07-24 | 1997-08-20 | 三菱電機株式会社 | 半導体装置の製造方法 |
| US5313367A (en) * | 1990-06-26 | 1994-05-17 | Seiko Epson Corporation | Semiconductor device having a multilayer interconnection structure |
| US5678301A (en) * | 1991-06-04 | 1997-10-21 | Micron Technology, Inc. | Method for forming an interconnect for testing unpackaged semiconductor dice |
| KR0153387B1 (ko) * | 1993-12-16 | 1998-12-01 | 가네꼬 히사시 | 칩 캐리어 반도체 디바이스 어셈블리 및 그 형성 방법 |
| JPH08236586A (ja) * | 1994-12-29 | 1996-09-13 | Nitto Denko Corp | 半導体装置及びその製造方法 |
| JPH08288424A (ja) * | 1995-04-18 | 1996-11-01 | Nec Corp | 半導体装置 |
| US6114763A (en) * | 1997-05-30 | 2000-09-05 | Tessera, Inc. | Semiconductor package with translator for connection to an external substrate |
| US6140707A (en) * | 1998-05-07 | 2000-10-31 | 3M Innovative Properties Co. | Laminated integrated circuit package |
| US6100112A (en) * | 1998-05-28 | 2000-08-08 | The Furukawa Electric Co., Ltd. | Method of manufacturing a tape carrier with bump |
| JP3843919B2 (ja) * | 2002-09-09 | 2006-11-08 | 株式会社デンソー | 半導体ウェハのめっき方法 |
| JP4108643B2 (ja) * | 2004-05-12 | 2008-06-25 | 日本電気株式会社 | 配線基板及びそれを用いた半導体パッケージ |
| JP5003812B2 (ja) | 2009-12-10 | 2012-08-15 | イビデン株式会社 | プリント配線板及びプリント配線板の製造方法 |
| JP6133227B2 (ja) * | 2014-03-27 | 2017-05-24 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
| JP2016122808A (ja) * | 2014-12-25 | 2016-07-07 | Ｓｈマテリアル株式会社 | 半導体装置用基板及びその製造方法 |
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2016
- 2016-07-12 JP JP2016137740A patent/JP6689691B2/ja active Active
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2017
- 2017-07-10 US US15/645,017 patent/US10170405B2/en active Active