JP2017528910A - マイクロエレクトロニクス基板上のドライハードマスク除去のための方法 - Google Patents
マイクロエレクトロニクス基板上のドライハードマスク除去のための方法 Download PDFInfo
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- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 18
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 claims description 11
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- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 8
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
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- B81C1/00595—Control etch selectivity
Abstract
Description
本出願は、2014年8月5日に出願された米国仮特許出願第62/033,347号の優先権を主張するものであり、その内容はすべて参照によりここに組み込まれる。
to)、複雑さも増し続けている。したがって、マイクロエレクトロニクスデバイスを製造するのに使用されるパターニング技術は、より小さいフィーチャを作成、製造中の膜への損傷を最小にするように、より正確になっている。フォトリソグラフィのためにより短い光波長にスケーリングすることが、より小型のデバイスを製造するための成功法であった。しかし、光波長のスケーリングは、マルチパターニング(MP)、自己整合型のダブル/クォドラプルパターニング(SADP/SAQP)のようなサブリソグラフィー技術を使用することによって克服できるいくらかの限界に達している。サブリソグラフィー技術は、デバイス製造をより小さい幾何学的形状に広げたが、デバイスの歩留まりを低下させるか、あるいは製造コストを増加させる可能性のある処理の複雑さも導入している。プロセスの複雑さは、より小さいデバイスフィーチャを可能にするために除去及び再塗布される必要がある可能性がある追加のフィルム層を含み得る。フィルム層の不完全な除去は、サブリソグラフィーパターニングに悪影響を及ぼし得る。これにより、下層膜上の上層膜の残留痕跡を除去するために膜層を除去することにより、パターニング結果を改善することができる。したがって、前述の問題を克服する可能性のある新しい処理技術が望まれ得る。
Claims (20)
- 基板を処理する方法であって、
プラズマ処理チャンバ内で前記基板を受ける工程であって、該基板は、有機含有層の上方のチタン含有層と、該有機含有層と該チタン含有層との間に配置されたハードマスク層とを含み、該チタン含有層及び該ハードマスク層は、該有機含有層の一部を露出させるようにパターニングされた、工程と、
塩素含有ガスと炭素含有ガスとを含む、第一比率のガス混合物を使用して、前記チタン含有層を処理する工程と、
第二比率の前記ガス混合物を使用して、前記チタン含有層を処理する工程と、
を含む方法。 - 前記第一比率を用いて処理する工程は、前記チタン含有層の表面からフッ化炭素と、前記チタン含有層の一部とを除去する、請求項1に記載の方法。
- 前記第二比率を用いて処理する工程は、前記チタン含有層を除去することによって、前記有機含有層を露出する、請求項2に記載の方法。
- 前記ガス混合物の第一比率は、前記塩素含有ガスと前記炭素含有ガスが約6:0.25である比率を含む、請求項1に記載の方法。
- 前記ガス混合物の第二比率は、前記塩素含有ガスと前記炭素含有ガスが約3:0.13である比率を含む、請求項1に記載の方法。
- 前記第一比率のガス混合物は、窒素含有ガス及びアルゴン含有ガスをさらに含み、前記第一比率は、前記塩素含有ガス、該窒素含有ガス、前記炭素含有ガス及び該アルゴン含有ガスが約6:1:0.25:8であることを含む、請求項1に記載の方法。
- 前記第二比率のガス混合物は、窒素含有ガス及びアルゴン含有ガスをさらに含み、前記第一比率は、前記塩素含有ガス、該窒素含有ガス、前記炭素含有ガス及び該アルゴン含有ガスが約3:0.0:0.13:4であることを含む、請求項1に記載の方法。
- 前記炭素含有ガスは、CH4又はC2H4の少なくとも一つを含み、前記塩素含有ガスは、Cl2、BCl3又はCCl4の少なくとも一つを含む、請求項1に記載の方法。
- 前記ハードマスク層は、酸化物、窒化ケイ素、又は炭化ケイ素を含む、請求項1に記載の方法。
- 前記チタン含有層の処理する工程は、10mTorrから30mTorrまでの圧力と前記プラズマ処理チャンバ内の少なくとも1つの電極に印加される100Wから1000Wまでの電力を含む、請求項1に記載の方法。
- 前記チタン含有層の処理する工程は、10mTorrから30mTorrまでの圧力、100℃までの温度、100Wから1000Wまでの電力及び150秒までのプロセス時間を含む、請求項1に記載の方法。
- 前記第一比率を使用して前記基板を処理する工程は、
上部電極と下部電極を含む前記プラズマ処理チャンバ内での約15mTorrの圧力と、
約350Wの上部電極電力と、
約30Wの下部電極電力と、
約30秒のプロセス時間と、
を含む、請求項1に記載の方法。 - 前記第二比率を使用して前記基板を処理する工程は、
上部電極と下部電極を含む前記プラズマ処理チャンバ内での約20mTorrの圧力と、
約350Wの上部電極電力と、
約30Wの下部電極電力と、
約90秒のプロセス時間と、
を含む、請求項1に記載の方法。 - 前記ハードマスク層は、酸化物、窒化ケイ素又は炭化ケイ素を含む、請求項1に記載の方法。
- 基板を処理する方法であって、
プラズマ処理チャンバ内で前記基板を受ける工程であって、該基板は、下層有機含有層と、金属含有層と、該下層有機含有層と該金属含有層との間に配置された誘電体層とを含み、該金属含有層は該金属含有層の露出面上のフッ化炭素要素を含む、工程と、
塩素含有ガスと炭素含有ガスとを含む、第一比率のガス混合物を含むプラズマを使用して、前記フッ化炭素要素を除去する工程と、
第二比率の前記ガス混合物を含むプラズマを使用して、前記金属含有層を除去する工程であって、該第二比率は前記第一比率とは異なる、工程と、を含む方法。
- 前記ガス混合物の第一比率は、前記塩素含有ガスと前記炭素含有ガスが約6:0.25である比率を含む、請求項15に記載の方法。
- 前記ガス混合物の第二比率は、前記塩素含有ガスと前記炭素含有ガスが約3:0.13である比率を含む、請求項15に記載の方法。
- 前記炭素含有ガスは、CH4又はC2H4の少なくとも一つを含む、請求項15に記載の方法。
- 前記塩素含有ガスは、Cl2、BCl3又はCCl4の少なくとも一つを含む、請求項18に記載の方法。
- 前記誘電体層は、酸化物、窒化ケイ素、又は炭化ケイ素を含む、請求項15に記載の方法。
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