JP2017517077A - メモリインターフェースのためのプログラマブル電力 - Google Patents

メモリインターフェースのためのプログラマブル電力 Download PDF

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Publication number
JP2017517077A
JP2017517077A JP2016570976A JP2016570976A JP2017517077A JP 2017517077 A JP2017517077 A JP 2017517077A JP 2016570976 A JP2016570976 A JP 2016570976A JP 2016570976 A JP2016570976 A JP 2016570976A JP 2017517077 A JP2017517077 A JP 2017517077A
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JP
Japan
Prior art keywords
update
delay
voltage bias
rate
pulse
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Pending
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JP2016570976A
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English (en)
Japanese (ja)
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JP2017517077A5 (enExample
Inventor
ディフェンダーファー、ジャン・クリスチャン
チェン、イェーチュン・クレア
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Qualcomm Inc
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Qualcomm Inc
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Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of JP2017517077A publication Critical patent/JP2017517077A/ja
Publication of JP2017517077A5 publication Critical patent/JP2017517077A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Pulse Circuits (AREA)
  • Dram (AREA)
JP2016570976A 2014-06-06 2015-05-11 メモリインターフェースのためのプログラマブル電力 Pending JP2017517077A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/298,730 US9443572B2 (en) 2014-06-06 2014-06-06 Programmable power for a memory interface
US14/298,730 2014-06-06
PCT/US2015/030214 WO2015187308A1 (en) 2014-06-06 2015-05-11 Programmable power for a memory interface

Publications (2)

Publication Number Publication Date
JP2017517077A true JP2017517077A (ja) 2017-06-22
JP2017517077A5 JP2017517077A5 (enExample) 2018-06-07

Family

ID=53268893

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016570976A Pending JP2017517077A (ja) 2014-06-06 2015-05-11 メモリインターフェースのためのプログラマブル電力

Country Status (11)

Country Link
US (1) US9443572B2 (enExample)
EP (1) EP3152762B1 (enExample)
JP (1) JP2017517077A (enExample)
KR (1) KR20170015909A (enExample)
CN (1) CN106663462B (enExample)
BR (1) BR112016028400A2 (enExample)
CA (1) CA2949492A1 (enExample)
ES (1) ES2713443T3 (enExample)
HU (1) HUE043506T2 (enExample)
TW (1) TW201610993A (enExample)
WO (1) WO2015187308A1 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9520864B2 (en) * 2014-06-06 2016-12-13 Qualcomm Incorporated Delay structure for a memory interface
KR102248279B1 (ko) * 2014-06-13 2021-05-07 삼성전자주식회사 불휘발성 메모리 및 메모리 컨트롤러를 포함하는 스토리지 장치, 그리고 불휘발성 메모리 및 메모리 컨트롤러 사이의 통신을 중개하는 리타이밍 회로의 동작 방법
US10177751B2 (en) * 2016-05-27 2019-01-08 Taiwan Semiconductor Manufacturing Company, Ltd. Delay line with short recovery time
CN112953530B (zh) * 2021-01-28 2024-02-23 星宸科技股份有限公司 除频器电路
JP2022146532A (ja) * 2021-03-22 2022-10-05 キオクシア株式会社 メモリシステム及び遅延制御方法
US11171654B1 (en) * 2021-05-13 2021-11-09 Qualcomm Incorporated Delay locked loop with segmented delay circuit
CN119690860B (zh) * 2023-09-22 2025-07-18 南京启见半导体科技有限公司 一种内存系统
TWI883683B (zh) * 2023-12-04 2025-05-11 群聯電子股份有限公司 電壓控制電路模組、記憶體儲存裝置及電壓控制方法

Citations (7)

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JP2001005554A (ja) * 1999-06-18 2001-01-12 Hitachi Ltd 半導体装置及びタイミング制御回路
JP2001250382A (ja) * 2000-03-03 2001-09-14 Hitachi Ltd クロック再生回路
US20070080728A1 (en) * 2005-10-12 2007-04-12 Toru Iwata Phase adjustment circuit
KR100839499B1 (ko) * 2006-12-22 2008-06-19 삼성전자주식회사 딜레이 제어 장치 및 방법
US20090085618A1 (en) * 2007-09-29 2009-04-02 Schneider Jacob S Wake-up circuit
US20100033217A1 (en) * 2008-08-08 2010-02-11 Chun Shiah Delayed-Locked Loop with power-saving function
US20130121094A1 (en) * 2011-11-15 2013-05-16 Rambus Inc. Integrated circuit comprising a delay-locked loop

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US6247138B1 (en) * 1997-06-12 2001-06-12 Fujitsu Limited Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system
PL343258A1 (en) 1998-03-16 2001-07-30 Jazio High speed signaling for interfacing vlsi cmos circuits
US6859109B1 (en) 2003-05-27 2005-02-22 Pericom Semiconductor Corp. Double-data rate phase-locked-loop with phase aligners to reduce clock skew
US9237000B2 (en) 2006-06-19 2016-01-12 Intel Corporation Transceiver clock architecture with transmit PLL and receive slave delay lines
US7795935B2 (en) * 2007-09-29 2010-09-14 Intel Corporation Bias signal delivery
KR20100097927A (ko) 2009-02-27 2010-09-06 삼성전자주식회사 지연 동기 루프 및 이를 포함하는 전자 장치
CN101713994B (zh) * 2009-12-03 2011-09-21 陕西北人印刷机械有限责任公司 印刷机在线生产信息管理系统及其方法
US9342095B2 (en) 2011-03-02 2016-05-17 Rambus Inc. Timing calibration for multimode I/O systems
US8624645B2 (en) * 2011-08-15 2014-01-07 Nanya Technology Corp. Multi phase clock signal generator, signal phase adjusting loop utilizing the multi phase clock signal generator, and multi phase clock signal generating method
US9041464B2 (en) 2011-09-16 2015-05-26 Qualcomm Incorporated Circuitry for reducing power consumption
US8836394B2 (en) 2012-03-26 2014-09-16 Rambus Inc. Method and apparatus for source-synchronous signaling

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001005554A (ja) * 1999-06-18 2001-01-12 Hitachi Ltd 半導体装置及びタイミング制御回路
JP2001250382A (ja) * 2000-03-03 2001-09-14 Hitachi Ltd クロック再生回路
US20070080728A1 (en) * 2005-10-12 2007-04-12 Toru Iwata Phase adjustment circuit
JP2007110323A (ja) * 2005-10-12 2007-04-26 Matsushita Electric Ind Co Ltd 位相調整回路
KR100839499B1 (ko) * 2006-12-22 2008-06-19 삼성전자주식회사 딜레이 제어 장치 및 방법
US20080150597A1 (en) * 2006-12-22 2008-06-26 Samsung Electronics Co., Ltd. Apparatus and methods for controlling delay using a delay unit and a phase locked loop
US20090085618A1 (en) * 2007-09-29 2009-04-02 Schneider Jacob S Wake-up circuit
US20100033217A1 (en) * 2008-08-08 2010-02-11 Chun Shiah Delayed-Locked Loop with power-saving function
US20130121094A1 (en) * 2011-11-15 2013-05-16 Rambus Inc. Integrated circuit comprising a delay-locked loop

Also Published As

Publication number Publication date
BR112016028400A2 (pt) 2017-08-22
KR20170015909A (ko) 2017-02-10
WO2015187308A1 (en) 2015-12-10
CN106663462B (zh) 2019-05-03
US9443572B2 (en) 2016-09-13
EP3152762A1 (en) 2017-04-12
CN106663462A (zh) 2017-05-10
US20150357017A1 (en) 2015-12-10
ES2713443T3 (es) 2019-05-21
EP3152762B1 (en) 2019-01-02
HUE043506T2 (hu) 2019-08-28
TW201610993A (zh) 2016-03-16
CA2949492A1 (en) 2015-12-10

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