JP2017517077A5 - - Google Patents
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- Publication number
- JP2017517077A5 JP2017517077A5 JP2016570976A JP2016570976A JP2017517077A5 JP 2017517077 A5 JP2017517077 A5 JP 2017517077A5 JP 2016570976 A JP2016570976 A JP 2016570976A JP 2016570976 A JP2016570976 A JP 2016570976A JP 2017517077 A5 JP2017517077 A5 JP 2017517077A5
- Authority
- JP
- Japan
- Prior art keywords
- data rate
- voltage bias
- rate
- pulse
- update
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000003111 delayed effect Effects 0.000 claims 6
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/298,730 US9443572B2 (en) | 2014-06-06 | 2014-06-06 | Programmable power for a memory interface |
| US14/298,730 | 2014-06-06 | ||
| PCT/US2015/030214 WO2015187308A1 (en) | 2014-06-06 | 2015-05-11 | Programmable power for a memory interface |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2017517077A JP2017517077A (ja) | 2017-06-22 |
| JP2017517077A5 true JP2017517077A5 (enExample) | 2018-06-07 |
Family
ID=53268893
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2016570976A Pending JP2017517077A (ja) | 2014-06-06 | 2015-05-11 | メモリインターフェースのためのプログラマブル電力 |
Country Status (11)
| Country | Link |
|---|---|
| US (1) | US9443572B2 (enExample) |
| EP (1) | EP3152762B1 (enExample) |
| JP (1) | JP2017517077A (enExample) |
| KR (1) | KR20170015909A (enExample) |
| CN (1) | CN106663462B (enExample) |
| BR (1) | BR112016028400A2 (enExample) |
| CA (1) | CA2949492A1 (enExample) |
| ES (1) | ES2713443T3 (enExample) |
| HU (1) | HUE043506T2 (enExample) |
| TW (1) | TW201610993A (enExample) |
| WO (1) | WO2015187308A1 (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9520864B2 (en) * | 2014-06-06 | 2016-12-13 | Qualcomm Incorporated | Delay structure for a memory interface |
| KR102248279B1 (ko) * | 2014-06-13 | 2021-05-07 | 삼성전자주식회사 | 불휘발성 메모리 및 메모리 컨트롤러를 포함하는 스토리지 장치, 그리고 불휘발성 메모리 및 메모리 컨트롤러 사이의 통신을 중개하는 리타이밍 회로의 동작 방법 |
| US10177751B2 (en) * | 2016-05-27 | 2019-01-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Delay line with short recovery time |
| CN112953530B (zh) * | 2021-01-28 | 2024-02-23 | 星宸科技股份有限公司 | 除频器电路 |
| JP2022146532A (ja) * | 2021-03-22 | 2022-10-05 | キオクシア株式会社 | メモリシステム及び遅延制御方法 |
| US11171654B1 (en) * | 2021-05-13 | 2021-11-09 | Qualcomm Incorporated | Delay locked loop with segmented delay circuit |
| CN119690860B (zh) * | 2023-09-22 | 2025-07-18 | 南京启见半导体科技有限公司 | 一种内存系统 |
| TWI883683B (zh) * | 2023-12-04 | 2025-05-11 | 群聯電子股份有限公司 | 電壓控制電路模組、記憶體儲存裝置及電壓控制方法 |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6247138B1 (en) * | 1997-06-12 | 2001-06-12 | Fujitsu Limited | Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system |
| PL343258A1 (en) | 1998-03-16 | 2001-07-30 | Jazio | High speed signaling for interfacing vlsi cmos circuits |
| JP4190662B2 (ja) * | 1999-06-18 | 2008-12-03 | エルピーダメモリ株式会社 | 半導体装置及びタイミング制御回路 |
| JP2001250382A (ja) * | 2000-03-03 | 2001-09-14 | Hitachi Ltd | クロック再生回路 |
| US6859109B1 (en) | 2003-05-27 | 2005-02-22 | Pericom Semiconductor Corp. | Double-data rate phase-locked-loop with phase aligners to reduce clock skew |
| JP4667196B2 (ja) * | 2005-10-12 | 2011-04-06 | パナソニック株式会社 | 位相調整回路 |
| US9237000B2 (en) | 2006-06-19 | 2016-01-12 | Intel Corporation | Transceiver clock architecture with transmit PLL and receive slave delay lines |
| KR100839499B1 (ko) * | 2006-12-22 | 2008-06-19 | 삼성전자주식회사 | 딜레이 제어 장치 및 방법 |
| US7795935B2 (en) * | 2007-09-29 | 2010-09-14 | Intel Corporation | Bias signal delivery |
| US7746135B2 (en) * | 2007-09-29 | 2010-06-29 | Intel Corporation | Wake-up circuit |
| TWI362836B (en) | 2008-08-08 | 2012-04-21 | Etron Technology Inc | Dll with power-saving function |
| KR20100097927A (ko) | 2009-02-27 | 2010-09-06 | 삼성전자주식회사 | 지연 동기 루프 및 이를 포함하는 전자 장치 |
| CN101713994B (zh) * | 2009-12-03 | 2011-09-21 | 陕西北人印刷机械有限责任公司 | 印刷机在线生产信息管理系统及其方法 |
| US9342095B2 (en) | 2011-03-02 | 2016-05-17 | Rambus Inc. | Timing calibration for multimode I/O systems |
| US8624645B2 (en) * | 2011-08-15 | 2014-01-07 | Nanya Technology Corp. | Multi phase clock signal generator, signal phase adjusting loop utilizing the multi phase clock signal generator, and multi phase clock signal generating method |
| US9041464B2 (en) | 2011-09-16 | 2015-05-26 | Qualcomm Incorporated | Circuitry for reducing power consumption |
| US9160350B2 (en) | 2011-11-15 | 2015-10-13 | Rambus Inc. | Integrated circuit comprising a delay-locked loop |
| US8836394B2 (en) | 2012-03-26 | 2014-09-16 | Rambus Inc. | Method and apparatus for source-synchronous signaling |
-
2014
- 2014-06-06 US US14/298,730 patent/US9443572B2/en active Active
-
2015
- 2015-05-11 ES ES15725168T patent/ES2713443T3/es active Active
- 2015-05-11 CN CN201580029466.7A patent/CN106663462B/zh active Active
- 2015-05-11 EP EP15725168.7A patent/EP3152762B1/en active Active
- 2015-05-11 HU HUE15725168A patent/HUE043506T2/hu unknown
- 2015-05-11 CA CA2949492A patent/CA2949492A1/en not_active Abandoned
- 2015-05-11 JP JP2016570976A patent/JP2017517077A/ja active Pending
- 2015-05-11 BR BR112016028400A patent/BR112016028400A2/pt not_active IP Right Cessation
- 2015-05-11 WO PCT/US2015/030214 patent/WO2015187308A1/en not_active Ceased
- 2015-05-11 KR KR1020167033909A patent/KR20170015909A/ko not_active Withdrawn
- 2015-05-20 TW TW104116143A patent/TW201610993A/zh unknown
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