JP2017505542A - 半導体活性区域及び隔離領域を形成するダブルパターン形成方法 - Google Patents
半導体活性区域及び隔離領域を形成するダブルパターン形成方法 Download PDFInfo
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- JP2017505542A JP2017505542A JP2016548019A JP2016548019A JP2017505542A JP 2017505542 A JP2017505542 A JP 2017505542A JP 2016548019 A JP2016548019 A JP 2016548019A JP 2016548019 A JP2016548019 A JP 2016548019A JP 2017505542 A JP2017505542 A JP 2017505542A
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- 238000000034 method Methods 0.000 title claims abstract description 56
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 238000002955 isolation Methods 0.000 title abstract description 54
- 239000000463 material Substances 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 66
- 229920002120 photoresistant polymer Polymers 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 6
- 239000011810 insulating material Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 238000012545 processing Methods 0.000 claims description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 229920005591 polysilicon Polymers 0.000 claims description 2
- 238000000059 patterning Methods 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 13
- 230000000873 masking effect Effects 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 238000012937 correction Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000012552 review Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3088—Process specially adapted to improve the resolution of the mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
Claims (10)
- 半導体基板を処理する方法であって、
基板表面上に第1の材料を形成することと、
前記第1の材料上に第2の材料を形成することと、
前記第2の材料中に複数の第1のトレンチであって、互いに平行である、複数の第1のトレンチを形成することと、
前記第2の材料中に第2のトレンチであって、前記基板の中心領域で前記複数の第1のトレンチと垂直であり、それらを横断する、第2のトレンチを形成することと、
前記第1及び第2のトレンチに第3の材料を充填することと、
前記第2の材料を除去して、互いに平行であり、前記基板の前記中心領域を通って延出しない第3のトレンチを前記第3の材料中に形成することと、
前記第3のトレンチを、前記第1の材料を通して前記基板内に延出させることと、を含む、方法。 - 前記第1の材料が二酸化ケイ素であり、前記第2の材料がポリシリコンである、請求項1に記載の方法。
- 前記第3の材料が二酸化ケイ素である、請求項2に記載の方法。
- 前記複数の第1のトレンチの前記形成が、
前記第2の材料上にフォトレジスト材料を形成することと、
前記フォトレジスト材料を選択的に除去して、前記第2の材料の列を露出させることと、
前記第2の材料の前記露出した列をエッチングで除去することと、を含む、請求項1に記載の方法。 - 前記第2のトレンチの前記形成が、
前記第2の材料上に第2のフォトレジスト材料を形成することと、
前記第2のフォトレジスト材料のストリップを選択的に除去して、前記第2の材料の行を露出させることと、
前記第2の材料の前記露出した行をエッチングで除去することと、を含む、請求項4に記載の方法。 - 前記第2の材料の前記除去が、前記第1の材料の部分を露出させる、請求項1に記載の方法。
- 前記第3のトレンチの前記延出が、
前記基板の部分が露出したままであるように、前記第1の材料の前記露出した部分をエッチングで除去することと、
前記基板の前記露出した部分にエッチングを実施することと、を含む、請求項6に記載の方法。 - 前記延出させた第3のトレンチに絶縁材料を充填することを更に含む、請求項1に記載の方法。
- 前記第3のトレンチの前記延出後に、
前記第3の材料を除去することと、
前記第1の材料を除去することと、を更に含む、請求項1に記載の方法。 - 前記第3及び第1の材料の前記除去の後に、
前記基板内の前記第3のトレンチに絶縁材料を充填することを更に含む、請求項9に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/162,309 US9293358B2 (en) | 2014-01-23 | 2014-01-23 | Double patterning method of forming semiconductor active areas and isolation regions |
US14/162,309 | 2014-01-23 | ||
PCT/US2014/070674 WO2015112282A1 (en) | 2014-01-23 | 2014-12-16 | Double patterning method of forming semiconductor active areas and isolation regions |
Publications (2)
Publication Number | Publication Date |
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JP2017505542A true JP2017505542A (ja) | 2017-02-16 |
JP6130079B2 JP6130079B2 (ja) | 2017-05-17 |
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JP2016548019A Active JP6130079B2 (ja) | 2014-01-23 | 2014-12-16 | 半導体活性区域及び隔離領域を形成するダブルパターン形成方法 |
Country Status (7)
Country | Link |
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US (1) | US9293358B2 (ja) |
EP (1) | EP3097581B1 (ja) |
JP (1) | JP6130079B2 (ja) |
KR (1) | KR101708606B1 (ja) |
CN (1) | CN106415816B (ja) |
TW (1) | TWI534947B (ja) |
WO (1) | WO2015112282A1 (ja) |
Families Citing this family (2)
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US9818722B1 (en) | 2016-08-05 | 2017-11-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Package structure and method for manufacturing thereof |
US10803227B2 (en) * | 2017-08-29 | 2020-10-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated circuit layouts with line-end extensions |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2003234422A (ja) * | 2001-12-27 | 2003-08-22 | Silicon Storage Technology Inc | 水平に向けたエッジをもつフローティングゲートメモリセルの半導体メモリアレーを形成するセルフ・アライン型方法及びそれにより形成されたメモリアレー |
JP2004064083A (ja) * | 2002-07-26 | 2004-02-26 | Samsung Electronics Co Ltd | 自己整列した接合領域コンタクトホールを有する半導体装置及びその製造方法 |
US20110248382A1 (en) * | 2008-12-30 | 2011-10-13 | Fabio Pellizzer | Double patterning method for creating a regular array of pillars with dual shallow trench isolation |
JP2012134395A (ja) * | 2010-12-22 | 2012-07-12 | Elpida Memory Inc | 半導体装置および半導体装置の製造方法 |
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US7315056B2 (en) | 2004-06-07 | 2008-01-01 | Silicon Storage Technology, Inc. | Semiconductor memory array of floating gate memory cells with program/erase and select gates |
US7429536B2 (en) * | 2005-05-23 | 2008-09-30 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US7879727B2 (en) | 2009-01-15 | 2011-02-01 | Infineon Technologies Ag | Method of fabricating a semiconductor device including a pattern of line segments |
KR101658492B1 (ko) * | 2010-08-13 | 2016-09-21 | 삼성전자주식회사 | 미세 패턴의 형성 방법 및 이를 이용한 반도체 소자의 제조 방법 |
CN102456577B (zh) | 2010-10-29 | 2014-10-01 | 中国科学院微电子研究所 | 应力隔离沟槽半导体器件的形成方法 |
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2014
- 2014-01-23 US US14/162,309 patent/US9293358B2/en active Active
- 2014-12-16 KR KR1020167022827A patent/KR101708606B1/ko active IP Right Grant
- 2014-12-16 JP JP2016548019A patent/JP6130079B2/ja active Active
- 2014-12-16 EP EP14822025.4A patent/EP3097581B1/en active Active
- 2014-12-16 WO PCT/US2014/070674 patent/WO2015112282A1/en active Application Filing
- 2014-12-16 CN CN201480073861.0A patent/CN106415816B/zh active Active
- 2014-12-24 TW TW103145236A patent/TWI534947B/zh active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003234422A (ja) * | 2001-12-27 | 2003-08-22 | Silicon Storage Technology Inc | 水平に向けたエッジをもつフローティングゲートメモリセルの半導体メモリアレーを形成するセルフ・アライン型方法及びそれにより形成されたメモリアレー |
JP2004064083A (ja) * | 2002-07-26 | 2004-02-26 | Samsung Electronics Co Ltd | 自己整列した接合領域コンタクトホールを有する半導体装置及びその製造方法 |
US20110248382A1 (en) * | 2008-12-30 | 2011-10-13 | Fabio Pellizzer | Double patterning method for creating a regular array of pillars with dual shallow trench isolation |
JP2012134395A (ja) * | 2010-12-22 | 2012-07-12 | Elpida Memory Inc | 半導体装置および半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
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JP6130079B2 (ja) | 2017-05-17 |
TW201532186A (zh) | 2015-08-16 |
KR20160104081A (ko) | 2016-09-02 |
EP3097581A1 (en) | 2016-11-30 |
CN106415816A (zh) | 2017-02-15 |
WO2015112282A1 (en) | 2015-07-30 |
CN106415816B (zh) | 2018-06-15 |
EP3097581B1 (en) | 2018-09-19 |
US9293358B2 (en) | 2016-03-22 |
US20150206788A1 (en) | 2015-07-23 |
KR101708606B1 (ko) | 2017-02-20 |
TWI534947B (zh) | 2016-05-21 |
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