JP2017208380A - 半導体装置および半導体装置の製造方法 - Google Patents
半導体装置および半導体装置の製造方法 Download PDFInfo
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Abstract
Description
関連する先行技術文献として下記の文献がある。
特許文献1 特開平9−266311号公報
特許文献2 特開2013−84899号公報
特許文献3 特許第4696335号公報
特許文献4 特開2010−114152号公報
図1は、本発明の第1実施例に係る半導体装置100の概要を示す断面図である。本例の半導体装置100はMOSFETであり、半導体基板10と、半導体基板10の上面側に形成されたドリフト領域12等の半導体領域と、半導体領域の上面側に形成されたソース電極50と、半導体基板10の下面側に形成されたドレイン電極52とを備える。
図4Aは、本発明の第2実施例に係る半導体装置200の概要を示す断面図である。図4Bは、本発明の第2実施例に係る半導体装置200の他の例を示す断面図である。図4Aに示す半導体装置200は、第1実施例に係る半導体装置100の構造に加え、第1導電型領域66を備える。本例の第1導電型領域66は、n型である。他の構造は、図1から図3において説明したいずれかの半導体装置100と同一であってよい。
Claims (18)
- 半導体基板と、
前記半導体基板の上面側に形成された第1導電型のドリフト領域と、
前記ドリフト領域の上方に形成された第2導電型のベース領域と、
前記ベース領域の上方に形成された第1導電型のソース領域と、
前記ソース領域の上端側から、前記ソース領域および前記ベース領域を貫通して形成された2以上のゲートトレンチと、
2つのゲートトレンチの間に形成され、前記ソース領域を貫通して、且つ、前記ベース領域に下端が配置されたコンタクトトレンチと、
前記コンタクトトレンチの下端と対向する領域において、前記ベース領域の下端の下側に突出して形成された第2導電型の突出部と
を備え、
前記ソース領域の上端から前記突出部の下端までの深さは3μm以上であり、
深さ方向と垂直な横方向において前記突出部と隣接する第1導電型の領域のキャリア濃度Ndと、前記突出部のキャリア濃度Naとが下式を満たす
- 前記ソース領域の上端から前記突出部の下端までの深さは15μm以下である
請求項1に記載の半導体装置。 - 前記コンタクトトレンチの下端から前記突出部の下端までの深さは14.7μm以下である
請求項1または2に記載の半導体装置。 - 前記コンタクトトレンチの下端と隣接して設けられ、前記ベース領域よりも不純物濃度が高い第2導電型の高濃度領域を更に備える
請求項1から3のいずれか一項に記載の半導体装置。 - 前記突出部の前記ベース領域の下端における幅は、前記コンタクトトレンチの幅の0.9倍以上、1.1倍以下である
請求項1から4のいずれか一項に記載の半導体装置。 - 少なくとも一つのゲートトレンチの下端と、前記突出部とに隣接して形成された、前記ドリフト領域よりも不純物濃度が高い第1導電型領域を更に備える
請求項1から5のいずれか一項に記載の半導体装置。 - 前記第1導電型領域と、前記ベース領域との間において、前記ゲートトレンチに隣接して形成され、前記第1導電型領域よりも不純物濃度が低い第1導電型の中間領域を更に備える
請求項6に記載の半導体装置。 - 前記中間領域の不純物濃度は、前記ドリフト領域の不純物濃度と等しい
請求項7に記載の半導体装置。 - 前記突出部の下端と、前記第1導電型領域の下端とが、同一の深さ位置に配置されている
請求項6から8のいずれか一項に記載の半導体装置。 - 前記ゲートトレンチの内壁に形成されたゲート絶縁膜と、
前記ゲートトレンチの内部において、前記ゲート絶縁膜に囲まれたゲート導電部と
を更に備え、
前記ゲート絶縁膜は、前記ゲートトレンチの下端に形成された部分が、前記ゲートトレンチの側壁に形成された部分よりも厚い
請求項6から9のいずれか一項に記載の半導体装置。 - 前記突出部の下端は、前記ゲートトレンチの下端よりも、前記ソース領域の上端からみて深い位置に配置されている
請求項1から10のいずれか一項に記載の半導体装置。 - それぞれのゲートトレンチと、前記突出部との距離は、0.4μm以上である
請求項1から11のいずれか一項に記載の半導体装置。 - 前記ソース領域の上方に形成されたソース電極を更に備え、
前記ソース電極は、前記コンタクトトレンチの内部にも形成され、
前記コンタクトトレンチの内壁と、前記ソース電極との間にバリアメタルを更に備える
請求項1から12のいずれか一項に記載の半導体装置。 - 半導体基板の上面側に、第1導電型のドリフト領域、第2導電型のベース領域、第1導電型のソース領域、および、前記ソース領域および前記ベース領域を貫通する2以上のゲートトレンチを形成する段階と、
2つのゲートトレンチの間に、前記ソース領域を貫通して、且つ、前記ベース領域に下端が配置されるコンタクトトレンチを形成する段階と、
前記コンタクトトレンチの下端から、前記ベース領域の下方に不純物を注入して、前記コンタクトトレンチの下端と対向する領域において、前記ベース領域の下端から下側に突出する第2導電型の突出部を形成する段階と
を備える半導体装置の製造方法。 - 前記コンタクトトレンチを形成する前に、前記ソース領域の上方に絶縁膜を形成し、
前記絶縁膜を貫通する前記コンタクトトレンチを形成する
請求項14に記載の半導体装置の製造方法。 - 前記突出部を形成する段階において、前記不純物を異なる深さにそれぞれ注入する
請求項14または15に記載の半導体装置の製造方法。 - 前記ゲートトレンチの下端から、前記ドリフト領域に不純物を注入して、前記ゲートトレンチの下端と、前記突出部とに隣接する、前記ドリフト領域よりも不純物濃度が高い第1導電型領域を形成する段階を更に備える
請求項14から17のいずれか一項に記載の半導体装置の製造方法。
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