JP2017147417A - 基板処理方法 - Google Patents
基板処理方法 Download PDFInfo
- Publication number
- JP2017147417A JP2017147417A JP2016030365A JP2016030365A JP2017147417A JP 2017147417 A JP2017147417 A JP 2017147417A JP 2016030365 A JP2016030365 A JP 2016030365A JP 2016030365 A JP2016030365 A JP 2016030365A JP 2017147417 A JP2017147417 A JP 2017147417A
- Authority
- JP
- Japan
- Prior art keywords
- gas
- wafer
- sio
- film
- silicon oxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims description 26
- 238000003672 processing method Methods 0.000 title claims description 15
- 239000007789 gas Substances 0.000 claims abstract description 116
- 238000005530 etching Methods 0.000 claims abstract description 40
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 23
- 239000001301 oxygen Substances 0.000 claims abstract description 22
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims description 36
- 229910000040 hydrogen fluoride Inorganic materials 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 34
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 22
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 21
- 239000007795 chemical reaction product Substances 0.000 claims description 11
- 238000005040 ion trap Methods 0.000 claims description 11
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 5
- 230000003213 activating effect Effects 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 4
- 229910052736 halogen Inorganic materials 0.000 claims description 4
- 150000002367 halogens Chemical class 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 3
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims description 2
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 2
- 150000001875 compounds Chemical class 0.000 claims description 2
- 239000011737 fluorine Substances 0.000 claims description 2
- 229910052731 fluorine Inorganic materials 0.000 claims description 2
- 239000001257 hydrogen Substances 0.000 claims description 2
- 229910052739 hydrogen Inorganic materials 0.000 claims description 2
- 150000002431 hydrogen Chemical class 0.000 claims description 2
- 229910052757 nitrogen Inorganic materials 0.000 claims description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 claims 1
- 229910001882 dioxygen Inorganic materials 0.000 claims 1
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 claims 1
- 239000002994 raw material Substances 0.000 claims 1
- 230000003746 surface roughness Effects 0.000 abstract description 7
- 229910004298 SiO 2 Inorganic materials 0.000 description 72
- 230000000052 comparative effect Effects 0.000 description 10
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 10
- 238000010438 heat treatment Methods 0.000 description 9
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000010926 purge Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910017855 NH 4 F Inorganic materials 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 239000006185 dispersion Substances 0.000 description 3
- 230000003028 elevating effect Effects 0.000 description 3
- 230000001678 irradiating effect Effects 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000011144 upstream manufacturing Methods 0.000 description 3
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 2
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000000654 additive Substances 0.000 description 2
- 230000000996 additive effect Effects 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 239000012159 carrier gas Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000010790 dilution Methods 0.000 description 2
- 239000012895 dilution Substances 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 239000002243 precursor Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 229940070337 ammonium silicofluoride Drugs 0.000 description 1
- 229910052786 argon Inorganic materials 0.000 description 1
- 230000002079 cooperative effect Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
- H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67017—Apparatus for fluid treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67155—Apparatus for manufacturing or treating in a plurality of work-stations
- H01L21/67161—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers
- H01L21/67167—Apparatus for manufacturing or treating in a plurality of work-stations characterized by the layout of the process chambers surrounding a central transfer chamber
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
- H01L21/68714—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support
- H01L21/68742—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches the wafers being placed on a susceptor, stage or support characterised by a lifting arrangement, e.g. lift pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Plasma & Fusion (AREA)
- Drying Of Semiconductors (AREA)
- Weting (AREA)
Abstract
【解決手段】
ウエハWの表面に形成されたSiO2膜1を下層に到達する前の途中段階までエッチングするにあたりSiO2膜1の表面に酸素ラジカル102を照射して親水化した後、NH3ガスとHFガスとにより、前記SiO2膜1をエッチングしている。そのためSiO2膜1の表面にNH3ガスとHFガスとを均一に吸着させることができる。従ってSiO2膜1の表面が一様にエッチングされ、SiO2膜1を下層に到達する前の途中段階までエッチングしたときにも表面の荒れ(ラフネス)を改善することができる。
【選択図】図4
Description
特許文献2には、基板表面に形成された酸化膜を除去するにあたって、エッチングの際の濡れ性を向上させるためにO2を活性化したプラズマを用いたプラズマ処理を行う技術が記載されているが、エッチング後の表面のラフネスについては、考慮していない。
前記シリコン酸化層の表面を親水化処理する第1の工程と、
次いでハロゲンを含むガスを前記基板に供給し、前記シリコン酸化層と反応して生成された反応生成物を昇華させることにより、前記シリコン酸化層をエッチングする第2の工程と、を含むことを特徴とする。
続いてウエハWを公知のCOR処理装置に搬送する。そしてSiO2膜1と、HF分子104及びNH3分子105とを反応させてSiO2膜1を除去するCOR(Chemical Oxide Removal)法によりエッチングを行う。COR処理装置においては、後述するようにウエハWにHFガス及びNH3ガスを供給する。これにより、HF分子104及びNH3分子105がSiO2膜1の表面に吸着する。
ラフネスが良好になる理由については、次のように推測される。図1に示すCMPを行ったウエハWにおけるSiO2膜1の表面においては、図5に示すようにアニール処理及びCMP処理の少なくとも一方の要因により、水酸基(OH基)101の多くが除去されて、SiO2分子の未結合手100が並んだ状態となっている。
アニール処理及びCMP処理を行った後においては、図5に示すようにウエハWの表面のOH基101がまばらになっている。そのためHFガス及びNH3ガスを供給したときに、ウエハWの表面においてOH基101が結合している部位に局所的にHF分子104及びNH3分子105が吸着してしまう。これに対してSiO2膜1の表面の表面に向けて酸素ラジカルを供給して、表面全体に一様にOH基101を分布させることにより、図8に示すようにHF分子104及びNH3分子105が均一に分布する。
また処理容器20の側壁には、イオントラップ板32と誘電体窓23との間にO2ガス及びArガスを供給するための処理容器20の内部に向かって開口した複数のガス供給口27が形成されている。ガス供給口27には、ガス供給管28が接続され、このガス供給管28は、例えばバルブV11、流量調整部M11を介してO2ガス供給源29に、バルブV12、流量調整部M12を介して添加ガスであるArガス供給源38に各々接続されている。
なおCOR処理装置9から搬出されたウエハWを真空搬送室64に接続された加熱処理室に搬入し、ここで例えばCOR処理装置9における加熱温度よりも高い温度でウエハWを加熱して、反応生成物106をより確実に昇華させるようにしてもよい。
またSiO2膜1をエッチングする手法としては、CORに限らずプラズマエッチングを行ってもよく、例えばNF3ガスとNH3ガスとを含む処理ガス、あるいはHFガスとNH3ガスをプラズマ化し、例えばプラズマをイオントラップ板32を通過させた後、ウエハWに供給するようにしてもよい。またエッチングにおいて、NH3ガスと共に用いられるガスとしては、HBrガスなどF以外のハロゲンを含むガスを用いてもよい。さらにNH3ガスに代えて、エタノール(C2H5OH)や水(H2O)を使用することもできる。
またSiO2膜1をすべて除去して、下層を露出させる場合においてもSiO2膜1のエッチングの際のラフネスが下層の表面に転写される可能性がある。そのためSiO2膜1をすべて除去する場合にも効果はある。
実施例として、ウエハWの表面に例えば有機原料ガスと、酸化ガスと、を用いたCVDによりSiO2膜を成膜し、次いで真空雰囲気中でN2ガスによりパージしながらウエハWを400〜1000℃で加熱してアニール処理を行う。さらにCMPにより表面の研磨を行って図1に示す試料を作成した。そして実施の形態と同様に図9に示すラジカル処理装置において試料に酸素ラジカルを180秒間供給する。その後図10に示すCOR処理装置を用いて、HFガス及びNH3ガスによりエッチング処理を行い、SiO2膜1に対して途中までエッチング処理を行った。また比較例として酸素ラジカルの照射を行わないことを除いて実施例と同様の処理を行った。
二乗平均粗さ(以下「平均粗さRMS」という)とは、粗さ曲線からその平均線の方向に基準長さlだけを抜き取り、基準長さlの平均線の方向にX軸を、縦倍率の方向にY軸を夫々取って、基準長さlの平均線から測定曲線までの偏差の二乗平均を合計した値である。粗さ曲線をy=f(x)で表すと、次式により求められる。
図12はこの結果を示し、実施例、比較例及び参考例における表面の平均粗さRMSの値を示す。なお図12中の誤差線は、AFM(原子間力顕微鏡)測定時の系統偏差を示す。また図13は、夫々参考例、比較例及び実施例におけるウエハWの表面を示す写真である。図12に示すように参考例においては、ウエハWの表面の平均粗さRMSは、0.298であったが、比較例では、3.108、実施例では、1.313であった。また図12に示すように参考例では、ほとんど凹凸が見られないのに対し、比較例では、大きな凹凸が見られ、実施例では、比較例よりも凹凸が小さくなっていることがわかる。
従って本発明によれば、SiO2膜1の表面をエッチングするにあたって、表面のラフネスの悪化を抑制することができると言える。
10 シリコン層
11 突壁部
12 溝部
13 第1のSiO2膜
14 第2のSiO2膜
101 OH基
102 O2ラジカル
104 HF分子
105 NH3分子
106 反応生成物
W ウエハ
Claims (8)
- 基板の表面部に形成されたシリコン酸化層をエッチングする基板処理方法において、
前記シリコン酸化層の表面を親水化処理する第1の工程と、
次いでハロゲンを含むガスを前記基板に供給し、前記シリコン酸化層と反応して生成された反応生成物を昇華させることにより、前記シリコン酸化層をエッチングする第2の工程と、を含むことを特徴とする基板処理方法。 - 前記第1の工程は、酸素の活性種を前記シリコン酸化層の表面に供給する工程であることを特徴とする請求項1に記載の基板処理方法。
- 前記酸素の活性種は酸素ラジカルであることを特徴とする請求項1または2に記載の基板処理方法。
- 前記第1の工程は、酸素ガス及びオゾンガスの少なくとも一方を活性化して得たプラズマを、複数のガス通過用の開口部が形成されたイオントラップ部材を通過させた後に前記シリコン酸化層の表面に供給する工程であることを特徴とする請求項2または3に記載の基板処理方法。
- 前記第2の工程は、フッ化水素ガスとアンモニアガスとを含む処理ガス、及び窒素、水素、フッ素を含む化合物を含む処理ガスのうちの少なくとも一方の処理ガスに基板の表面を曝す工程であることを特徴とする請求項1ないし4のいずれか一項に記載の基板処理方法。
- 前記第2の工程は、三フッ化窒素ガスまたはフッ化水素ガスと、アンモニアガスと、の混合ガスを活性化して得られたプラズマにより前記基板に対してエッチングを行うことを特徴とする請求項1ないし4のいずれか一項に記載の基板処理方法。
- 前記シリコン酸化層は、原料ガスと酸化ガスとを反応させて堆積したものであることを特徴とする請求項1ないし6のいずれか一項に記載の基板処理方法
- 前記シリコン酸化層の表面を親水化処理する工程の前に、
前記シリコン酸化層をアニール処理する工程と、
次いで前記シリコン酸化層を研磨して平坦化する平坦化処理と、を含むことを特徴とする請求項1ないし7のいずれか一項に記載の基板処理方法。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016030365A JP6601257B2 (ja) | 2016-02-19 | 2016-02-19 | 基板処理方法 |
SG11201806972RA SG11201806972RA (en) | 2016-02-19 | 2017-02-07 | Substrate treatment method |
KR1020187026810A KR102244356B1 (ko) | 2016-02-19 | 2017-02-07 | 기판 처리 방법 |
CN201780011940.2A CN108701599B (zh) | 2016-02-19 | 2017-02-07 | 基板处理方法 |
PCT/JP2017/004431 WO2017141773A1 (ja) | 2016-02-19 | 2017-02-07 | 基板処理方法 |
TW106104923A TWI702647B (zh) | 2016-02-19 | 2017-02-15 | 基板處理方法 |
US15/999,361 US10923358B2 (en) | 2016-02-19 | 2017-02-17 | Substrate processing method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016030365A JP6601257B2 (ja) | 2016-02-19 | 2016-02-19 | 基板処理方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2017147417A true JP2017147417A (ja) | 2017-08-24 |
JP6601257B2 JP6601257B2 (ja) | 2019-11-06 |
Family
ID=59625859
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2016030365A Active JP6601257B2 (ja) | 2016-02-19 | 2016-02-19 | 基板処理方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US10923358B2 (ja) |
JP (1) | JP6601257B2 (ja) |
KR (1) | KR102244356B1 (ja) |
CN (1) | CN108701599B (ja) |
SG (1) | SG11201806972RA (ja) |
TW (1) | TWI702647B (ja) |
WO (1) | WO2017141773A1 (ja) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020008954A1 (ja) * | 2018-07-04 | 2020-01-09 | 東京エレクトロン株式会社 | 基板処理方法及び基板処理装置 |
JP7459720B2 (ja) | 2020-08-11 | 2024-04-02 | 東京エレクトロン株式会社 | シリコン酸化膜をエッチングする方法、装置及びシステム |
TWI838381B (zh) | 2018-07-04 | 2024-04-11 | 日商東京威力科創股份有限公司 | 基板處理方法及基板處理裝置 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20200060559A (ko) * | 2018-11-20 | 2020-06-01 | 세메스 주식회사 | 본딩 장치 및 본딩 방법 |
JP7414593B2 (ja) * | 2020-03-10 | 2024-01-16 | 東京エレクトロン株式会社 | 基板処理方法及び基板処理装置 |
JP2023184336A (ja) * | 2022-06-17 | 2023-12-28 | 株式会社Kokusai Electric | 基板処理方法、半導体装置の製造方法、基板処理装置、およびプログラム |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08327959A (ja) * | 1994-06-30 | 1996-12-13 | Seiko Epson Corp | ウエハ及び基板の処理装置及び処理方法、ウエハ及び基板の移載装置 |
JP2009545460A (ja) * | 2006-08-02 | 2009-12-24 | ポイント 35 マイクロストラクチャーズ リミテッド | 犠牲酸化ケイ素層をエッチングする方法 |
JP2012235059A (ja) * | 2011-05-09 | 2012-11-29 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
JP2016025111A (ja) * | 2014-07-16 | 2016-02-08 | 東京エレクトロン株式会社 | 基板洗浄方法、基板処理方法、基板処理システム、および半導体装置の製造方法 |
Family Cites Families (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4845054A (en) * | 1985-06-14 | 1989-07-04 | Focus Semiconductor Systems, Inc. | Low temperature chemical vapor deposition of silicon dioxide films |
JP3237743B2 (ja) | 1996-02-15 | 2001-12-10 | 東京エレクトロン株式会社 | プラズマ処理装置及びプラズマ処理方法 |
DE10109218A1 (de) * | 2001-02-26 | 2002-06-27 | Infineon Technologies Ag | Verfahren zur Herstellung eines Speicherkondensators |
JP2003068766A (ja) | 2001-08-28 | 2003-03-07 | Murata Mfg Co Ltd | 電界効果トランジスタの製造方法 |
KR100628888B1 (ko) * | 2004-12-27 | 2006-09-26 | 삼성전자주식회사 | 샤워 헤드 온도 조절 장치 및 이를 갖는 막 형성 장치 |
JP5374039B2 (ja) | 2007-12-27 | 2013-12-25 | 東京エレクトロン株式会社 | 基板処理方法、基板処理装置及び記憶媒体 |
JP2009156774A (ja) | 2007-12-27 | 2009-07-16 | Chugoku Electric Power Co Inc:The | 流量監視方法、流量監視装置 |
EP2409313A1 (de) * | 2009-03-17 | 2012-01-25 | Roth & Rau AG | Substratbearbeitungsanlage und substratbearbeitungsverfahren |
JP5522979B2 (ja) * | 2009-06-16 | 2014-06-18 | 国立大学法人東北大学 | 成膜方法及び処理システム |
US20110139748A1 (en) * | 2009-12-15 | 2011-06-16 | University Of Houston | Atomic layer etching with pulsed plasmas |
JP5701654B2 (ja) * | 2011-03-23 | 2015-04-15 | 東京エレクトロン株式会社 | 基板処理方法 |
JP5926527B2 (ja) * | 2011-10-17 | 2016-05-25 | 信越化学工業株式会社 | 透明soiウェーハの製造方法 |
JP5398853B2 (ja) * | 2012-01-26 | 2014-01-29 | 東京エレクトロン株式会社 | プラズマ処理方法及びプラズマ処理装置 |
TWI604528B (zh) * | 2012-10-02 | 2017-11-01 | 應用材料股份有限公司 | 使用電漿預處理與高溫蝕刻劑沉積的方向性二氧化矽蝕刻 |
JP6211999B2 (ja) * | 2014-06-25 | 2017-10-11 | 株式会社東芝 | 窒化物半導体層、窒化物半導体装置及び窒化物半導体層の製造方法 |
US9431268B2 (en) | 2015-01-05 | 2016-08-30 | Lam Research Corporation | Isotropic atomic layer etch for silicon and germanium oxides |
-
2016
- 2016-02-19 JP JP2016030365A patent/JP6601257B2/ja active Active
-
2017
- 2017-02-07 WO PCT/JP2017/004431 patent/WO2017141773A1/ja active Application Filing
- 2017-02-07 KR KR1020187026810A patent/KR102244356B1/ko active IP Right Grant
- 2017-02-07 CN CN201780011940.2A patent/CN108701599B/zh active Active
- 2017-02-07 SG SG11201806972RA patent/SG11201806972RA/en unknown
- 2017-02-15 TW TW106104923A patent/TWI702647B/zh active
- 2017-02-17 US US15/999,361 patent/US10923358B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08327959A (ja) * | 1994-06-30 | 1996-12-13 | Seiko Epson Corp | ウエハ及び基板の処理装置及び処理方法、ウエハ及び基板の移載装置 |
JP2009545460A (ja) * | 2006-08-02 | 2009-12-24 | ポイント 35 マイクロストラクチャーズ リミテッド | 犠牲酸化ケイ素層をエッチングする方法 |
JP2012235059A (ja) * | 2011-05-09 | 2012-11-29 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
JP2016025111A (ja) * | 2014-07-16 | 2016-02-08 | 東京エレクトロン株式会社 | 基板洗浄方法、基板処理方法、基板処理システム、および半導体装置の製造方法 |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2020008954A1 (ja) * | 2018-07-04 | 2020-01-09 | 東京エレクトロン株式会社 | 基板処理方法及び基板処理装置 |
JP2020009835A (ja) * | 2018-07-04 | 2020-01-16 | 東京エレクトロン株式会社 | 基板処理方法及び基板処理装置 |
KR20210024108A (ko) * | 2018-07-04 | 2021-03-04 | 도쿄엘렉트론가부시키가이샤 | 기판 처리 방법 및 기판 처리 장치 |
JP7137976B2 (ja) | 2018-07-04 | 2022-09-15 | 東京エレクトロン株式会社 | 基板処理方法及び基板処理装置 |
KR102571843B1 (ko) * | 2018-07-04 | 2023-08-28 | 도쿄엘렉트론가부시키가이샤 | 기판 처리 방법 및 기판 처리 장치 |
TWI838381B (zh) | 2018-07-04 | 2024-04-11 | 日商東京威力科創股份有限公司 | 基板處理方法及基板處理裝置 |
JP7459720B2 (ja) | 2020-08-11 | 2024-04-02 | 東京エレクトロン株式会社 | シリコン酸化膜をエッチングする方法、装置及びシステム |
Also Published As
Publication number | Publication date |
---|---|
US10923358B2 (en) | 2021-02-16 |
KR102244356B1 (ko) | 2021-04-23 |
US20190109012A1 (en) | 2019-04-11 |
KR20180116327A (ko) | 2018-10-24 |
JP6601257B2 (ja) | 2019-11-06 |
CN108701599A (zh) | 2018-10-23 |
WO2017141773A1 (ja) | 2017-08-24 |
TW201742134A (zh) | 2017-12-01 |
TWI702647B (zh) | 2020-08-21 |
SG11201806972RA (en) | 2018-09-27 |
CN108701599B (zh) | 2023-04-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI648791B (zh) | Etching method | |
KR101974715B1 (ko) | 산화막 제거 방법 및 제거 장치, 및 콘택 형성 방법 및 콘택 형성 시스템 | |
JP6601257B2 (ja) | 基板処理方法 | |
US10256107B2 (en) | Substrate processing method | |
US8956546B2 (en) | Substrate processing method and substrate processing apparatus | |
KR102441239B1 (ko) | 에칭 방법 | |
CN110783188B (zh) | 蚀刻方法和蚀刻装置 | |
TW201608605A (zh) | 改質處理方法及半導體裝置之製造方法 | |
JP7401593B2 (ja) | 空隙を形成するためのシステム及び方法 | |
CN110663098A (zh) | 利用聚合物结构去活化工艺的选择性沉积工艺 | |
US11996296B2 (en) | Substrate processing method and substrate processing system | |
US11557486B2 (en) | Etching method, damage layer removal method, and storage medium | |
JP7294999B2 (ja) | エッチング方法 | |
US9646818B2 (en) | Method of forming planar carbon layer by applying plasma power to a combination of hydrocarbon precursor and hydrogen-containing precursor | |
WO2011055671A1 (ja) | 成膜方法およびキャパシタの形成方法 | |
TWI751326B (zh) | 自對準通孔處理流程 | |
JP7209567B2 (ja) | エッチング方法およびエッチング装置 | |
US20220189783A1 (en) | Etching method and etching apparatus | |
WO2024070685A1 (ja) | 成膜方法、成膜装置、および成膜システム | |
JP2022094914A (ja) | エッチング方法およびエッチング装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160225 |
|
RD02 | Notification of acceptance of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: A7422 Effective date: 20180117 |
|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20180827 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20190604 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20190802 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20190910 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20190923 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6601257 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |