JP2017037964A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2017037964A JP2017037964A JP2015158364A JP2015158364A JP2017037964A JP 2017037964 A JP2017037964 A JP 2017037964A JP 2015158364 A JP2015158364 A JP 2015158364A JP 2015158364 A JP2015158364 A JP 2015158364A JP 2017037964 A JP2017037964 A JP 2017037964A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 183
- 230000006378 damage Effects 0.000 abstract description 6
- 238000009413 insulation Methods 0.000 abstract 4
- 239000012535 impurity Substances 0.000 description 20
- 230000004048 modification Effects 0.000 description 11
- 238000012986 modification Methods 0.000 description 11
- 238000000034 method Methods 0.000 description 7
- 230000015556 catabolic process Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 230000020169 heat generation Effects 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
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Abstract
Description
一方で、半導体装置を高温環境下で使用した場合には、熱による半導体装置の破壊が懸念される。
第2半導体領域は、第1部分を有する。複数の第2半導体領域は、第1半導体領域の上に設けられている。
第3半導体領域は、第2半導体領域の上に選択的に設けられている。第3半導体領域は、第1半導体領域から第2半導体領域に向かう第1方向に対して垂直な第2方向において、第1部分と並んでいる。
絶縁部は、複数の第2半導体領域の間に設けられている。絶縁部の一方の側は、第1部分に接している。絶縁部の他方の側は、第3半導体領域に接している。
第1電極は、絶縁部に囲まれている。第1電極の少なくとも一部は、第1半導体領域に囲まれている。
ゲート電極は、第1電極と離間して設けられている。ゲート電極は、絶縁部に囲まれている。ゲート電極は、第2方向において第2半導体領域と対面している。
第2電極は、第3半導体領域の上に設けられている。第2電極は、第1電極および第3半導体領域と電気的に接続されている。
なお、図面は模式的または概念的なものであり、各部分の厚みと幅との関係、部分間の大きさの比率などは、必ずしも現実のものと同一とは限らない。また、同じ部分を表す場合であっても、図面により互いの寸法や比率が異なって表される場合もある。
また、本願明細書と各図において、既に説明したものと同様の要素には同一の符号を付して詳細な説明は適宜省略する。
各実施形態の説明には、XYZ直交座標系を用いる。半導体層Sの表面に対して平行な方向であって相互に直交する2方向をX方向(第2方向)及びY方向(第3方向)とし、これらX方向及びY方向の双方に対して直交する方向をZ方向(第1方向)とする。
以下の説明において、n+、n−及びp+、pの表記は、各導電形における不純物濃度の相対的な高低を表す。すなわち、n+はn−よりもn形の不純物濃度が相対的に高いことを示す。また、p+はpよりもp形の不純物濃度が相対的に高いことを示す。
以下で説明する各実施形態について、各半導体領域のp形とn形を反転させて各実施形態を実施してもよい。
図1を用いて、第1実施形態に係る半導体装置の一例について説明する。
図1は、第1実施形態に係る半導体装置100の一部を表す斜視断面図である。
半導体装置100は、n+形(第1導電形)のドレイン領域5と、n−形半導体領域1(第1半導体領域)と、p形(第2導電形)のベース領域2(第2半導体領域)と、n+形ソース領域3(第3半導体領域)と、絶縁部20と、フィールドプレート電極11(第1電極)と、ゲート電極12と、ドレイン電極31と、ソース電極32(第2電極)と、を有する。
n+形ドレイン領域5は、半導体層S中の裏面BS側に設けられている。n+形ドレイン領域5は、ドレイン電極31と電気的に接続されている。
n−形半導体領域1の上には、p形ベース領域2が選択的に設けられている。p形ベース領域2はX方向において複数設けられ、それぞれのp形ベース領域2はY方向に延びている。
p形ベース領域2は、表面FS側に設けられた第1部分2aを有する。第1部分2aのp形不純物濃度は、p形ベース領域2の他の部分のp形不純物濃度と等しくてもよいし、これより高くてもよい。
n+形ソース領域3は、X方向において、p形ベース領域2の第1部分2aと並んでいる。第1部分2aとn+形ソース領域3は、X方向において交互に並んでいる。
FP電極11は、絶縁部20を介してn−形半導体領域1に囲まれている。
ゲート電極12はFP電極11の上に設けられ、X方向において絶縁部20を介してp形ベース領域2と対面している。ゲート電極12は、Z方向(n−形半導体領域1からp形ベース領域2に向かう方向)において、FP電極11と離間している。
FP電極11、ゲート電極12、および絶縁部20は、X方向において複数設けられ、それぞれがY方向に延びている。
図2および図3は、第1実施形態に係る半導体装置100の製造工程を表す工程断面図である。
以下では、n+形半導体層5aおよびn−形半導体層1aの主成分がシリコンである場合について説明する。
その後、n+形ドレイン領域5の下にドレイン電極31を形成することで、図1に表す半導体装置100が得られる。
本実施形態によれば、半導体装置のオン抵抗を低減しつつ、熱による半導体装置の破壊を抑制することができる。
半導体装置がFP電極11を有することで、半導体装置の耐圧を高めることができる。このため、FP電極11によって耐圧が向上した分、n−形半導体領域1の不純物濃度を高め、半導体装置のオン抵抗を低減することができる。
このとき、よりFP電極11同士の間隔が狭いほど、n−形半導体領域1の不純物濃度を高くすることができる。
ただし、図1に表す、第1部分2aおよびn+形ソース領域3がX方向において交互に並べられている場合の方が、2つの第1部分2aおよび2つのn+形ソース領域3がX方向において交互に並べられている場合に比べて、電流経路同士の重なりをより小さくすることができ、n−形半導体領域1における発熱をより一層抑制することが可能である。
図4を用いて、第1実施形態の変形例に係る半導体装置の一例について説明する。
図4は、第1実施形態の変形例に係る半導体装置110の一部を表す断面図である。
具体的には、図4に表すように、半導体装置110は、X方向において互いに離間して並べられた、FP電極11、ゲート電極12aおよび12bを有する。ゲート電極12aおよび12bは、FP電極11とそれぞれのp形ベース領域2との間に設けられている。
すなわち、図1に表す半導体装置100によれば、本変形例に係る半導体装置110に比べて、ゲート電極12に電圧の印加を開始してからゲート電極12に閾値以上の電圧が印加されるまでの、半導体装置のターンオン時間を短縮することができる。
一方で、チャネル密度を高めることで、上述した通り、電流経路の重なりによる発熱量の増加が生じる。従って、第1部分2aを設けることによる半導体装置の発熱量の抑制は、FP電極11とゲート電極12がZ方向において並んだ半導体装置100に対してより有効である。
従って、本変形例は、上述したようなゲート電極12のピッチおよびn−形半導体領域1の不純物濃度を有する半導体装置に対して特に有効である。
図5を用いて、第2実施形態に係る半導体装置の一例について説明する。
図5は、第2実施形態に係る半導体装置200の一部を表す断面図である。
あるいは、第1電極部分32aと絶縁部20との間に第1部分2aが設けられておらず、第1電極部分32aが絶縁部20と接していてもよい。
まず、図2(a)〜図3(a)に表す工程と同様の工程を実行する。続いて、p形ベース領域2およびn+形ソース領域3を形成する。続いて、p形ベース領域2のうち、n+形ソース領域3が設けられていない領域の一部を除去し、トレンチを形成する。
半導体装置200をターンオフした際、半導体装置200のインダクタンスによりドレイン電極31にはサージ電圧が加わる。このサージ電圧によりp形ベース領域2の電位が上昇すると、半導体装置200に含まれる寄生バイポーラトランジスタがラッチアップする場合がある。半導体装置が高温環境下で用いられる場合、寄生バイポーラトランジスタがラッチアップした際に流れる電流も大きく、この電流によって半導体装置がさらに発熱するため、熱によって半導体装置が破壊される可能性が高くなる。
このため、絶縁部20の両側にn+形ソース領域が設けられている場合に比べて、p形ベース領域2とソース電極32との間の電気抵抗をより一層低減することが可能となる。
また、各半導体領域における不純物濃度については、例えば、SIMS(二次イオン質量分析法)により測定することが可能である。
Claims (6)
- 第1導電形の第1半導体領域と、
第1部分を有し、前記第1半導体領域の上に設けられた第2導電形の複数の第2半導体領域と、
前記第2半導体領域の上に選択的に設けられ、前記第1半導体領域から前記第2半導体領域に向かう第1方向に対して垂直な第2方向において前記第1部分と並ぶ第1導電形の第3半導体領域と、
前記複数の第2半導体領域の間に設けられ、一方の側が前記第1部分に接し、他方の側が前記第3半導体領域に接する絶縁部と、
前記絶縁部に囲まれ、少なくとも一部が前記第1半導体領域に囲まれた第1電極と、
前記第1電極と離間して設けられ、前記絶縁部に囲まれ、前記第2方向において前記第2半導体領域と対面するゲート電極と、
前記第3半導体領域の上に設けられ、前記第1電極および前記第3半導体領域と電気的に接続された第2電極と、
を備えた半導体装置。 - 前記絶縁部は、
前記第1方向および前記第2方向に対して垂直な第3方向と、前記第1方向と、に沿う第1面と、
前記第1面と反対側の第2面と、
を有し、
前記第1面は、前記第1部分に接し、
前記第2面は、前記第3半導体領域に接する請求項1記載の半導体装置。 - 前記第2電極は、前記第2方向において、前記第3半導体領域と前記第1部分との間に設けられた第1電極部分を有する請求項1または2に記載の半導体装置。
- 前記第2半導体領域と前記第1電極部分との間に設けられた第2導電形の第4半導体領域をさらに備え、
前記第4半導体領域の第2導電形のキャリア濃度は、前記第2半導体領域の第2導電形のキャリア濃度よりも高い請求項3記載の半導体装置。 - 前記第3半導体領域、前記絶縁部、前記第1電極、および前記ゲート電極は、前記第2方向において複数設けられ、
それぞれの前記第3半導体領域は、それぞれの前記第2半導体領域の上に選択的に設けられ、
前記第1部分および前記第3半導体領域は、前記第2方向において交互に並べられ、
それぞれの前記絶縁部は、前記第2半導体領域同士の間に設けられ、それぞれの前記絶縁部の一方の側はそれぞれの前記第3半導体領域に接し、それぞれの前記絶縁部の他方の側はそれぞれの前記第1部分に接し、
それぞれの前記第1電極およびそれぞれの前記ゲート電極は、それぞれの前記絶縁部に囲まれた請求項1記載の半導体装置。 - 前記複数のゲート電極のピッチは、2.0μm以下であり、
前記第1半導体領域の第1導電形のキャリア濃度は、1.0×1016atm/cm3以上である請求項5記載の半導体装置。
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