JP2016519443A - 安定した高移動度のｍｏｔｆｔおよび低温での製作 - Google Patents

安定した高移動度のｍｏｔｆｔおよび低温での製作 Download PDF

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JP2016519443A
JP2016519443A JP2016515344A JP2016515344A JP2016519443A JP 2016519443 A JP2016519443 A JP 2016519443A JP 2016515344 A JP2016515344 A JP 2016515344A JP 2016515344 A JP2016515344 A JP 2016515344A JP 2016519443 A JP2016519443 A JP 2016519443A
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layer
amorphous
high mobility
metal oxide
depositing
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JP2016519443A5 (https=
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シェ，チャン−ロン
ユ，ガン
フーン，ファット
ミュソッフ，ユルゲン
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CBRITE Inc
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CBRITE Inc
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    • H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
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    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/673—Thin-film transistors [TFT] characterised by the electrodes characterised by the shapes, relative sizes or dispositions of the gate electrodes
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    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
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    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
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    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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    • H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/22—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using physical deposition, e.g. vacuum deposition or sputtering
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    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3434—Deposited materials, e.g. layers characterised by the chemical composition being oxide semiconductor materials
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    • H10P70/23—Cleaning during device manufacture during, before or after processing of insulating materials
    • H10P70/234—Cleaning during device manufacture during, before or after processing of insulating materials the processing being the formation of vias or contact holes
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    • H10D86/021—Manufacture or treatment of multiple TFTs

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  • Thin Film Transistor (AREA)
  • Formation Of Insulating Films (AREA)
  • Physical Vapour Deposition (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2016515344A 2013-05-24 2014-05-07 安定した高移動度のｍｏｔｆｔおよび低温での製作 Pending JP2016519443A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US13/902,514 US9356156B2 (en) 2013-05-24 2013-05-24 Stable high mobility MOTFT and fabrication at low temperature
US13/902,514 2013-05-24
PCT/US2014/037191 WO2014189681A2 (en) 2013-05-24 2014-05-07 Stable high mobility motft and fabrication at low temperature

Publications (2)

Publication Number Publication Date
JP2016519443A true JP2016519443A (ja) 2016-06-30
JP2016519443A5 JP2016519443A5 (https=) 2017-12-07

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JP2016515344A Pending JP2016519443A (ja) 2013-05-24 2014-05-07 安定した高移動度のｍｏｔｆｔおよび低温での製作

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US (2) US9356156B2 (https=)
EP (1) EP3005420A4 (https=)
JP (1) JP2016519443A (https=)
KR (1) KR20160012165A (https=)
CN (1) CN105308753A (https=)
WO (1) WO2014189681A2 (https=)

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JP2017143135A (ja) * 2016-02-09 2017-08-17 株式会社ジャパンディスプレイ 薄膜トランジスタ
KR20200069472A (ko) * 2018-12-07 2020-06-17 연세대학교 산학협력단 산화물 반도체 박막 트랜지스터
WO2022249872A1 (ja) * 2021-05-26 2022-12-01 株式会社ニコン 半導体装置、電子デバイス、ｐＨセンサ、バイオセンサ、半導体装置の製造方法、及び電子デバイスの製造方法

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US9515158B1 (en) * 2015-10-20 2016-12-06 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor structure with insertion layer and method for manufacturing the same
US9496415B1 (en) 2015-12-02 2016-11-15 International Business Machines Corporation Structure and process for overturned thin film device with self-aligned gate and S/D contacts
KR102448587B1 (ko) * 2016-03-22 2022-09-28 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치, 및 상기 반도체 장치를 포함하는 표시 장치
US10461197B2 (en) 2016-06-03 2019-10-29 Semiconductor Energy Laboratory Co., Ltd. Sputtering target, oxide semiconductor, oxynitride semiconductor, and transistor
CN107749422A (zh) * 2017-09-21 2018-03-02 信利（惠州）智能显示有限公司 氧化物半导体薄膜晶体管
CN112005383A (zh) 2018-03-12 2020-11-27 株式会社半导体能源研究所 金属氧化物以及包含金属氧化物的晶体管
CN109638070B (zh) * 2018-12-12 2021-01-15 广州新视界光电科技有限公司 氧化物半导体材料、薄膜晶体管及制备方法和显示面板

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JP2012514328A (ja) * 2008-12-24 2012-06-21 スリーエム イノベイティブ プロパティズ カンパニー 金属酸化物半導体薄膜トランジスタにおける安定性の向上
JP2010161327A (ja) * 2009-01-12 2010-07-22 Samsung Mobile Display Co Ltd 有機電界発光表示装置及びその製造方法
JP2010165922A (ja) * 2009-01-16 2010-07-29 Idemitsu Kosan Co Ltd 電界効果型トランジスタ、電界効果型トランジスタの製造方法及び半導体素子の製造方法
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2017143135A (ja) * 2016-02-09 2017-08-17 株式会社ジャパンディスプレイ 薄膜トランジスタ
KR20200069472A (ko) * 2018-12-07 2020-06-17 연세대학교 산학협력단 산화물 반도체 박막 트랜지스터
KR102163565B1 (ko) * 2018-12-07 2020-10-12 연세대학교 산학협력단 산화물 반도체 박막 트랜지스터
WO2022249872A1 (ja) * 2021-05-26 2022-12-01 株式会社ニコン 半導体装置、電子デバイス、ｐＨセンサ、バイオセンサ、半導体装置の製造方法、及び電子デバイスの製造方法
JPWO2022249872A1 (https=) * 2021-05-26 2022-12-01
JP7632606B2 (ja) 2021-05-26 2025-02-19 株式会社ニコン 半導体装置、電子デバイス、ｐＨセンサ、バイオセンサ、半導体装置の製造方法、及び電子デバイスの製造方法

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US20140346495A1 (en) 2014-11-27
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