JP2016510185A5 - - Google Patents

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JP2016510185A5
JP2016510185A5 JP2015557231A JP2015557231A JP2016510185A5 JP 2016510185 A5 JP2016510185 A5 JP 2016510185A5 JP 2015557231 A JP2015557231 A JP 2015557231A JP 2015557231 A JP2015557231 A JP 2015557231A JP 2016510185 A5 JP2016510185 A5 JP 2016510185A5
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base
nodes
punctured
ldpc code
bits
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JP2015557231A
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JP6542132B2 (ja
JP2016510185A (ja
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JP2015557231A 2013-02-13 2014-02-13 高レート、高並列性、および低エラーフロアのために、疑似巡回構成を使用し、パンクチャするｌｄｐｃ設計 Active JP6542132B2 (ja)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US201361764476P 2013-02-13 2013-02-13
US61/764,476 2013-02-13
US14/179,942 US9306601B2 (en) 2013-02-13 2014-02-13 LDPC design for high parallelism, low error floor, and simple encoding
PCT/US2014/016261 WO2014127129A1 (en) 2013-02-13 2014-02-13 Ldpc design using quasi-cyclic constructions and puncturing for high rate, high parallelism, and low error floor
US14/179,871 2014-02-13
US14/179,942 2014-02-13
US14/179,871 US20140229788A1 (en) 2013-02-13 2014-02-13 Ldpc design for high rate, high parallelism, and low error floor

Publications (3)

Publication Number Publication Date
JP2016510185A JP2016510185A (ja) 2016-04-04
JP2016510185A5 true JP2016510185A5 (enExample) 2017-02-23
JP6542132B2 JP6542132B2 (ja) 2019-07-10

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JP2015557231A Active JP6542132B2 (ja) 2013-02-13 2014-02-13 高レート、高並列性、および低エラーフロアのために、疑似巡回構成を使用し、パンクチャするｌｄｐｃ設計
JP2015557232A Active JP5976960B2 (ja) 2013-02-13 2014-02-13 高並列性、低エラーフロア、および簡単な符号化原理を有するリフトされたｌｄｐｃ符号のための設計

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JP2015557232A Active JP5976960B2 (ja) 2013-02-13 2014-02-13 高並列性、低エラーフロア、および簡単な符号化原理を有するリフトされたｌｄｐｃ符号のための設計

Country Status (7)

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US (2) US9306601B2 (enExample)
EP (2) EP2957037A1 (enExample)
JP (2) JP6542132B2 (enExample)
KR (2) KR101662747B1 (enExample)
CN (2) CN105075128B (enExample)
BR (1) BR112015019409B1 (enExample)
WO (2) WO2014127140A1 (enExample)

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