US20140229788A1 - Ldpc design for high rate, high parallelism, and low error floor - Google Patents

Ldpc design for high rate, high parallelism, and low error floor Download PDF

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US20140229788A1
US20140229788A1 US14/179,871 US201414179871A US2014229788A1 US 20140229788 A1 US20140229788 A1 US 20140229788A1 US 201414179871 A US201414179871 A US 201414179871A US 2014229788 A1 US2014229788 A1 US 2014229788A1
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base
nodes
punctured
ldpc code
bits
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Thomas Joseph Richardson
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Qualcomm Inc
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Qualcomm Inc
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Priority to BR112015019409-5A priority Critical patent/BR112015019409B1/pt
Priority to PCT/US2014/016261 priority patent/WO2014127129A1/en
Priority to KR1020157024378A priority patent/KR101662747B1/ko
Priority to KR1020157024376A priority patent/KR102142142B1/ko
Priority to JP2015557231A priority patent/JP6542132B2/ja
Priority to PCT/US2014/016279 priority patent/WO2014127140A1/en
Priority to CN201480008409.6A priority patent/CN104981978B/zh
Priority to CN201480008419.XA priority patent/CN105075128B/zh
Priority to JP2015557232A priority patent/JP5976960B2/ja
Priority to US14/179,871 priority patent/US20140229788A1/en
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Assigned to QUALCOMM INCORPORATED reassignment QUALCOMM INCORPORATED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: RICHARDSON, THOMAS JOSEPH
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    • H03—ELECTRONIC CIRCUITRY
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    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
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    • H—ELECTRICITY
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    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/033—Theoretical methods to calculate these checking codes
    • H03M13/036—Heuristic code construction methods, i.e. code construction or code search based on using trial-and-error
    • H—ELECTRICITY
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    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1105—Decoding
    • H03M13/1131—Scheduling of bit node or check node processing
    • H03M13/1137—Partly parallel processing, i.e. sub-blocks or sub-groups of nodes being processed in parallel
    • H—ELECTRICITY
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    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
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    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
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    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
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    • H03M13/1168—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices wherein the sub-matrices have column and row weights greater than one, e.g. multi-diagonal sub-matrices
    • H—ELECTRICITY
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    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/118—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure
    • H03M13/1185—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal
    • H03M13/1188—Parity check matrix structured for simplifying encoding, e.g. by having a triangular or an approximate triangular structure wherein the parity-check matrix comprises a part with a double-diagonal wherein in the part with the double-diagonal at least one column has an odd column weight equal or greater than three
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/611—Specific encoding aspects, e.g. encoding by means of decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/63—Joint error correction and other techniques
    • H03M13/635—Error control coding in combination with rate matching
    • H03M13/6362—Error control coding in combination with rate matching by puncturing

Definitions

  • the present embodiments relate generally to communications and data storage systems, and specifically to communications and data storage systems that use LDPC codes.
  • LDPC codes are a particular type of error correcting codes which use an iterative coding system.
  • LDPC codes can be represented by bipartite graphs (often referred to as “Tanner graphs”), wherein a set of variable nodes corresponds to bits of a codeword, and a set of check nodes correspond to a set of parity-check constraints that define the code.
  • a variable node and a check node are considered “neighbors” if they are connected by an edge in the graph.
  • a bit sequence having a one-to-one association with the variable node sequence is a valid codeword if and only if, for each check node, the bits associated with all neighboring variable nodes sum to zero modulo two (i.e., they include an even number of 1's).
  • FIG. 1A shows a bipartite graph 100 representing an exemplary LDPC code.
  • the bipartite graph 100 includes a set of 5 variable nodes 110 (represented by circles) connected to 4 check nodes 120 (represented by squares). Edges in the graph 100 connect variable nodes 110 to the check nodes 120 .
  • FIG. 1B shows a matrix representation 150 of the bipartite graph 100 .
  • FIG. 2 graphically illustrates the effect of making three copies of the graph of FIG.
  • a received LDPC codeword can be decoded to produce a reconstructed version of the original codeword.
  • decoding can be used to recover the original data unit that was encoded.
  • LDPC decoder(s) generally operate by exchanging messages within the bipartite graph 100 , along the edges, and updating these messages by performing computations at the nodes based on the incoming messages. For example, each variable node 110 in the graph 100 may initially be provided with a “soft bit” (e.g., representing the received bit of the codeword) that indicates an estimate of the associated bit's value as determined by observations from the communications channel.
  • the LDPC decoders may update messages by iteratively reading them, or some portion thereof, from memory and writing an updated message, or some portion thereof, back to, memory.
  • the update operations are typically based on the parity check constraints of the corresponding LDPC code.
  • messages on like edges are often processed in parallel.
  • LDPC codes designed for high speed applications often use quasi-cyclic constructions with large lifting factors and relatively small base graphs to support high parallelism in encoding and decoding operations.
  • LDPC codes with higher code rates tend to have relatively fewer parity checks. If the number of base parity checks is smaller than the degree of a variable node (e.g., the number of edges connected to a variable node), then, in the base graph, that variable node is connected to at least one of the base parity checks by two or more edges (e.g., the variable node may have a “double edge”).
  • Having a based variable node and a base check node connected by two or more edges is generally undesirable for parallel hardware implementation purposes.
  • double edges may result in multiple concurrent read and write operations to the same memory locations, which in turn may create data coherency problems.
  • Pipelining of parallel message updates can be adversely affected by the presence of double edges.
  • a device and method of operation are disclosed that may aid in the encoding and/or decoding of low density parity check (LDPC) codewords.
  • LDPC low density parity check
  • an encoder may receive a set of information bits and perform an LDPC encoding operation on the information bits to produce a codeword.
  • the device may then puncture a set of lifted codeword bits corresponding to one or more base variable nodes based on a lifted LDPC code used for the LDPC encoding operation, wherein the punctured bits correspond with one or more punctured base variable nodes, respectively, of the base LDPC graph.
  • punctured variable nodes in the graphical description of the code can be eliminated from the description by a check node combining process operating on the lifted parity check matrix. Therefore, at least one of the one or more punctured base nodes is understood to eliminate multiple edges between node pairs of the base graph for the lifted LDPC code when the elimination of the punctured variable node results in multiple edges.
  • the one or more punctured nodes may include a variable node having a degree equal to, or one less than, a number of check nodes of the LDPC code.
  • at least one of the punctured nodes may be a highest-degree variable node of the LDPC code.
  • the high degree of the node is often desirable for enhancing the performance of the code.
  • the puncturing allows higher variable node degree while avoiding double edges in the base graph. The presence of the punctured variable node in the graph effectively increases the number of check nodes that would otherwise be present in a base graph of a code of the same size and rate.
  • At least one of the punctured nodes may be a degree two variable node used to split a check node that would otherwise be connected to a variable node of the LDPC code by two or more edges.
  • a punctured degree two node can be eliminated from the description by adding the two parity checks to which it is connected.
  • the at least one punctured base degree two variable node may thus be used to eliminate double edges in the base LDPC graph.
  • a high degree punctured node may be eliminated from a parity check matrix representation by an elimination process summing constraint nodes to effectively reduce the degree of the variable node to one.
  • a degree one punctured node can be eliminated from the graph along with its neighboring check node without altering the code. Such an elimination process is likely to introduce double or multiple edges into the representation which is undesirable for parallel implementation of decoding.
  • the present embodiments may reduce the complexity of the hardware that performs LDPC decoding operations in parallel, thereby increasing the processing efficiency of LDPC decoders that implement lifted LDPC codes. This further simplifies read and/or write operations performed in memory, and ensures that the read and write operations are not performed out of order. By allowing larger variable node degrees, while avoiding double edges, the present embodiments may also improve the error correcting performance of the LDPC coding system.
  • FIGS. 1A-1B show graphical and matrix representations of an exemplary LDPC code
  • FIG. 2 graphically illustrates the effect of making three copies of the graph of FIG. 1A ;
  • FIG. 3 shows a communications system in accordance with some embodiments
  • FIG. 4 is a block diagram of a communications device in accordance with some embodiments.
  • FIG. 5 is an illustrative flow chart depicting an LDPC encoding operation in accordance with some embodiments
  • FIG. 6 is an illustrative flow chart depicting an LDPC decoding operation in accordance with some embodiments
  • FIG. 10 is a block diagram of a communications device in accordance with some embodiments.
  • circuit elements or software blocks may be shown as buses or as single signal lines.
  • Each of the buses may alternatively be a single signal line, and each of the single signal lines may alternatively be buses, and a single line or bus might represent any one or more of a myriad of physical or logical mechanisms for communication between components.
  • the present embodiments are not to be construed as limited to specific examples described herein but rather to include within their scope all embodiments defined by the appended claims.
  • FIG. 3 shows a communications system 300 in accordance with some embodiments.
  • a transmitter 310 transmits a signal onto a channel 320
  • a receiver 330 receives the signal from the channel 320 .
  • the transmitter 310 and receiver 330 may be, for example, computers, switches, routers, hubs, gateways, and/or similar devices.
  • the channel 320 is wireless.
  • the channel 320 is a wired link (e.g., a coaxial cable or other physical connection).
  • Imperfections of various components in the communications system 300 may become sources of signal impairment, and thus cause signal degradation.
  • imperfections in the channel 320 may introduce channel distortion, which may include linear distortion, multi-path effects, and/or Additive White Gaussian Noise (AWGN).
  • the transmitter 310 and the receiver 330 may include LDPC encoders and decoders. Specifically, the transmitter 310 may perform LDPC encoding on outgoing data to produce a codeword that can be subsequently decoded by the receiver 330 (e.g., through an LDPC decoding operation) to recover the original data. For some embodiments, the transmitter 310 may transmit LDPC-encoded codewords with one or more “punctured” bits, for example, based on an LDPC code with one or more punctured variable nodes.
  • Lifting enables LDPC codes to be implemented using parallel encoding and/or decoding implementations while also reducing the complexity typically associated with large LDPC codes. More specifically, lifting is a technique for generating a relatively large LDPC code from multiple copies of a smaller base code. For example, a lifted LDPC code may be generated by producing a number (Z) of parallel copies of the base graph and then interconnecting the parallel copies through permutations of edge clusters of each copy of the base graph.
  • Z number
  • a more detailed discussion of lifted LDPC codes may be found, for example, in the book titled, “Modern Coding Theory,” published Mar. 17, 2008, by Tom Richardson and Ruediger Urbanke, which is hereby incorporated by reference in its entirety.
  • an LDPC decoder may utilize Z processing elements to perform parity check or variable node operations on all Z edges of a lifted graph concurrently.
  • each parity check operation may involve reading a corresponding soft bit value from memory, combining the soft bit value with other soft bit values associated with the check node and writing a soft bit back to memory that results from the check node operation.
  • Double edges in the base graph may trigger parallel reading of the same soft bit value, in a memory location, twice during a single parallel parity check update. Additional circuitry may thus be needed to combine the soft bit values that are written back to memory, so as to properly incorporate both updates. Eliminating double edges in the base graph helps to avoid this extra complexity.
  • the puncturing may reduce the complexity of the hardware that performs parallel check node or variable node operations, thereby increasing the parallel processing efficiency of a corresponding LDPC decoder. This further simplifies read and/or write operations performed in memory, and ensures that the read and write operations are not performed out of order.
  • Puncturing is the act of removing bits from a codeword to yield a shorter codeword.
  • Puncturing a variable node in an LDPC code creates a shortened code (e.g. due to the removal of a bit), while also effectively removing a check node.
  • Puncturing the variable node removes the associated bit from the code and effectively removes its single neighboring check node from the graph.
  • the number of check nodes in the graph is reduced by one. If the base transmitted block length is n ⁇ p, where p is the number of punctured columns, and the number of base parity checks is m, then the rate is (n ⁇ m)/(n ⁇ p). The binary information block size is (n ⁇ m)*Z, and the transmitted block size is (n ⁇ p)*Z. Note that if we increase n and p by 1 we may increase m by 1 and leave the rate and block size unchanged.
  • a punctured degree-two variable node effectively merges its two neighboring check nodes into a single check node.
  • the punctured degree two variable node effectively indicates that its two neighboring check nodes have, absent the degree two node, the same parity.
  • punctured degree-two variable nodes may be used to “split” check nodes, thereby appearing to increase the total number of check nodes. This mechanism may therefore be used to remove multiple edges from an LDPC code.
  • a variable node is typically connected to at least one check node by two or more edges if the degree of the variable node is greater than the total number of check nodes (N) in the base graph.
  • N total number of check nodes
  • Puncturing a high degree base variable node of the LDPC code can also increase the number of check nodes.
  • high degree check nodes can be desirable in high performing LDPC design.
  • the highest degree variable node may correspond to a variable node having a degree equal to (or one less than) the total number of check nodes in the base graph.
  • Such a high degree variable node can evidently be present in a base graph without any double edges.
  • a punctured variable node is treated as “erased” at decoding.
  • high degree punctured variable nodes in the graph may improve the performance of the code. It is known that punctured nodes in a graph can improve the so-called iterative threshold of the code structure. In standard irregular LDPC designs (i.e., without punctured variable nodes), thresholds can be improved by increasing the average degree in the bipartite graph, and thus increasing the degrees of the variable and check nodes. With punctured variable nodes, the same effect may be achieved with lower average degree, thereby reducing the complexity of the LDPC code. Furthermore, LDPC code structures having lower average degrees may perform better on smaller graphs. Thus, puncturing high-degree variable nodes may both increase the number of check nodes (thus allowing higher degrees) and improve the performance of codes with limited maximum variable node degrees.
  • FIG. 4 is a block diagram of a communications device 400 in accordance with some embodiments.
  • the communications device 400 includes an encoder 410 , a decoder 420 , and a transceiver 430 , which transmits and/or receives LDPC-encoded codewords via a communications channel.
  • the encoder 410 includes a memory 412 , and an LDPC encoder 414 .
  • the memory 412 may be used to store data (i.e., information bits) to be encoded by the LDPC encoder 414 .
  • the LDPC encoder 414 processes the information bits stored in the memory 412 by generating codewords, based on an LDPC code, to be transmitted to another device.
  • the LDPC code may be a lifted LDPC code.
  • the base LDPC code may include one or more punctured nodes.
  • the LDPC encoder 414 may thus puncture one or more bits of the codeword which correspond with respective punctured nodes of the base LDPC code. These punctured codeword bits are not transmitted by the transceiver 430 .
  • the punctured nodes may include a base variable node having a degree equal to, or one less than, a number of check nodes of the LDPC code.
  • at least one of the punctured nodes may be a highest-degree variable node of the LDPC code.
  • At least one of the punctured nodes may be used to split a check node that is connected to a variable node of the LDPC code by two or more edges.
  • Such a punctured node may be used to eliminate double edges in the base graph for the lifted LDPC code.
  • the decoder 420 includes a memory 422 and an LDPC decoder 424 .
  • the memory 422 stores codewords, received via the transceiver 430 , to be decoded by the LDPC decoder 424 .
  • the LDPC decoder 424 processes the codewords stored in the memory 424 by iteratively performing parity check operations, using an LDPC code, and attempting correcting any bits that may have been received in error.
  • the LDPC code may be a lifted LDPC code.
  • the received codeword may include one or more puncture bits as determined, for example, based on a set of punctured nodes of the corresponding LDPC code. As described above, with reference to FIG.
  • the punctured nodes may be determined based on the degrees of the variable nodes of the LDPC code.
  • the LDPC decoder 424 may thus treat these punctured nodes as erased for purposes of decoding. For example, the LDPC decoder 424 may set the log-likelihood ratios (LLRs) of the punctured nodes to zero at initialization.
  • LLRs log-likelihood ratios
  • the LDPC decoder 424 may include a plurality of processing elements to perform the parity check or variable node operations in parallel. For example, when processing a codeword with lifting size Z, the LDPC decoder 424 may utilize a number (Z) of processing elements to perform parity check operations on all Z edges of a lifted graph, concurrently. Specifically, each parity check operation may involve reading a corresponding soft bit value from memory 422 , combining the soft bit value with other soft bit values associated with the check node and writing a soft bit back to memory 422 that results from the check node operation.
  • a double edge in a base LDPC code may trigger parallel reading of the same soft bit value memory location twice during a single parallel parity check update. Thus, additional circuitry is typically needed to combine the soft bit values that are written back to memory, so as to properly incorporate both updates. However, eliminating double edges in the LDPC code, for example, as described above with respect to FIG. 3 , helps to avoid this extra complexity.
  • FIG. 5 is an illustrative flow chart depicting an LDPC encoding operation 500 in accordance with some embodiments.
  • the encoder 410 first receives a set of information bits to be encoded ( 510 ).
  • the information bits may correspond to data intended to be transmitted to another device (e.g., a receiving device) over a communications channel or network.
  • the information bits may be received from a central processing unit (CPU) and stored in memory 412 .
  • CPU central processing unit
  • the encoder 410 may then perform an LDPC encoding operation on the information bits to produce an LDPC codeword ( 520 ).
  • the LDPC encoder 414 may encode the information bits into LDPC codewords based on an LDPC code that is shared by the encoder 410 and a corresponding decoder (e.g., of the receiving device).
  • Each codeword may include the original information bits, or a portion thereof, as well as a set of parity bits which may be used (e.g., by the decoder) to perform parity check operations on and/or recover the original information bits.
  • the encoder 410 may further puncture one or more bits of the LDPC codeword based on base punctured variable nodes of the LDPC code ( 530 ).
  • the one or more punctured codeword bits may correspond with one or more base variable punctured nodes, respectively, of the base LDPC code.
  • at least some of the punctured nodes are provided to eliminate multiple edges between node pairs in the base graph of the lifted LDPC code.
  • the punctured nodes may include a variable node having a degree equal to, or one less than, a number of check nodes of the LDPC code.
  • at least one of the punctured nodes may be a degree 2 variable node.
  • the degree 2 variable node may be used to split a check node that would otherwise be connected to another variable node of the LDPC code by two or more edges. For some embodiments both may occur, specifically, both a high degree punctured variable node and a degree two punctured node may occur in the base graph.
  • the LDPC code may be a lifted LDPC code. Still further, the LDPC code may be based on a quasi-cycling lifting, wherein the permutations of edge clusters are cyclic permutations.
  • FIG. 6 is an illustrative flow chart depicting an LDPC decoding operation 600 in accordance with some embodiments.
  • the decoder 420 first receives an LDPC codeword to be decoded ( 610 ).
  • the LDPC codeword may be received from a transmitting device, for example, in the form of a quadrature amplitude modulated (QAM) data signal. Accordingly, the LDPC codeword may correspond with a subset of labeling bits of the de-mapped QAM data signal.
  • QAM quadrature amplitude modulated
  • the decoder 420 may identify one or more punctured bits of the LDPC codeword based on base punctured nodes of the LDPC code ( 620 ).
  • the one or more punctured codeword bits may correspond with one or more base punctured nodes, respectively, of the LDPC code.
  • the base punctured nodes are provided to eliminate multiple edges between node pairs in the base graph of the lifted LDPC code.
  • the punctured nodes may include a variable node having a degree equal to, or one less than, a number of check nodes of the LDPC code.
  • at least one of the punctured nodes may be a degree 2 variable node.
  • the degree 2 variable node may be used to split a check node that would otherwise be connected to another variable node of the LDPC code by two or more edges.
  • the LDPC code may be a lifted LDPC code (e.g., based on a quasi-cyclic lifting).
  • the decoder 420 may then perform an LDPC decoding operation on the received codeword to recover the original information bits ( 630 ).
  • the LDPC decoder 424 may process the codeword by iteratively performing parity check operations, using the LDPC code, and attempting to correct any bits that may have been received in error.
  • the LDPC decoder 424 may treat the punctured codeword bits as erased during the decoding operation, for example, by setting the LLRs of the punctured nodes to zero at initialization.
  • each of the LDPC codes may be viewed as a two dimensional binary array of size Z ⁇ n, where n is the base (transmission) block length.
  • k is a factor of 360, and k bits may be taken at a time columnwise, thus generating 360/k dimensions or 180/k symbols per column. It should thus be noted that k is a factor of 60 for the set k ⁇ 1, 2, 3, 4, 5, 6 ⁇ , in the cases of interest.
  • FIGS. 7 , 8 , and 9 show exemplary parity check matrices 700 , 800 , and 900 , respectively, in accordance with some embodiments.
  • the top row indexes columns of H.
  • the second row indicates information (1) and parity (0) columns.
  • the third row indicates transmitted columns (1) and punctured columns (0).
  • the parity check matrix 700 has a punctured degree two variable node (index 0). Such a node may split a single parity check into two. This ensures that the base matrix has no double edges, and facilitates some of the embodiments described herein.
  • An equivalent code representation can be constructed by merging the two parity checks and eliminating the punctured degree 2 variable node. Moreover, such an equivalent representation shall have double or multiple edges in the base graph.
  • FIG. 10 is a block diagram of a communications device 1000 in accordance with some embodiments.
  • the communications device 1000 includes a transceiver 1010 , a processor 1020 , and memory 1030 .
  • the transceiver 1010 may be used for communicating data to and/or from the communications device 1000 .
  • the transceiver 1010 may receive and/or transmit information bits between the communications device 1000 and a CPU.
  • the encoder interface 1010 may also output and/or receive LDPC codewords between the communications device 1000 and another communications device in a network.
  • Memory 1030 may include a data store 1032 that may be used as a local cache to store the received information bits and/or codewords. Furthermore, memory 1030 may also include a non-transitory computer-readable storage medium (e.g., one or more nonvolatile memory elements, such as EPROM, EEPROM, Flash memory, a hard drive, etc.) that can store the following software modules:
  • a non-transitory computer-readable storage medium e.g., one or more nonvolatile memory elements, such as EPROM, EEPROM, Flash memory, a hard drive, etc.
  • the processor 1020 which is coupled between the encoder interface 1010 and the memory 1030 , may be any suitable processor capable of executing scripts of instructions of one or more software programs stored in the decoder 1000 (e.g., within memory 1030 ).
  • the processor 1020 may execute the LDPC encoding module 1034 and/or the LDPC decoding module 1036 .
  • the LDPC encoding module 1034 may be executed by the processor 1020 to encode the information bits, using the LDPC code, to produce a codeword.
  • the processor 1020 in executing the LDPC encoding module 1034 , may perform an LDPC encoding operation on the information bits based on an LDPC code that is shared by the LDPC encoding module 1034 and a decoding module of a corresponding receive device.
  • Each codeword may include the original information bits as well as a set of parity bits which may be used to perform parity checks on and/or recover the original information bits.
  • the LDPC code may be a lifted LDPC code (e.g., based on a quasi-cyclic lifting).
  • the processor 1020 in executing the LDPC encoding module 1034 , may further puncture one or more bits of the codeword based on the corresponding LDPC code.
  • the one or more punctured codeword bits may correspond with one or more punctured nodes, respectively, of the LDPC code.
  • the punctured nodes are provided to eliminate multiple edges between node pairs in the base graph for the lifted LDPC code.
  • the punctured nodes may include a variable node having a degree equal to, or one less than, a number of check nodes of the LDPC code.
  • at least one of the punctured nodes may be a degree 2 variable node (e.g., used to split a check node that would otherwise be connected to another variable node of the LDPC code by two or more edges).
  • the LDPC decoding module 1036 may be executed by the processor 1020 to decode LDPC codewords using the LDPC code.
  • the processor 1020 in executing the LDPC decoding module 1036 , may first identify one or more punctured bits of the received codeword based on the LDPC code. The processor 1020 may then perform an LDPC decoding operation on the received codeword, while treating the punctured codeword bits as erased.
  • the LDPC decoding module 1036 as executed by the processor 1020 , may set the LLRs of the punctured nodes to zero at initialization.
  • the LDPC code may be a lifted LDPC code (e.g., based on a quasi-cyclic lifting).
  • the punctured codeword bits may correspond with respective punctured nodes of the LDPC code, wherein at least some of the punctured nodes are provided to eliminate multiple edges between node pairs in the base graph for the lifted LDPC code.
  • the punctured nodes may include a variable node having a degree equal to, or one less than, a number of check nodes of the LDPC code.
  • at least one of the punctured nodes may be a degree 2 variable node (e.g., used to split a check node that would otherwise be connected to another variable node of the LDPC code by two or more edges).

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JP2015557232A JP5976960B2 (ja) 2013-02-13 2014-02-13 高並列性、低エラーフロア、および簡単な符号化原理を有するリフトされたｌｄｐｃ符号のための設計
KR1020157024378A KR101662747B1 (ko) 2013-02-13 2014-02-13 높은 병렬성, 낮은 에러 플로어, 및 간단한 인코딩 원리를 갖는 리프팅된 ldpc 코드들에 대한 설계
KR1020157024376A KR102142142B1 (ko) 2013-02-13 2014-02-13 높은 레이트, 높은 병렬성, 및 낮은 에러 플로어를 위해 준순환 구조들 및 펑처링을 사용하는 ldpc 설계
JP2015557231A JP6542132B2 (ja) 2013-02-13 2014-02-13 高レート、高並列性、および低エラーフロアのために、疑似巡回構成を使用し、パンクチャするｌｄｐｃ設計
PCT/US2014/016279 WO2014127140A1 (en) 2013-02-13 2014-02-13 Design for lifted ldpc codes having high parallelism, low error floor, and simple encoding principle
BR112015019409-5A BR112015019409B1 (pt) 2013-02-13 2014-02-13 Projeto de ldpc utilizando construções quase-cíclicas e perfuração para alta taxa, alto paralelismo, e piso de erro baixo
CN201480008419.XA CN105075128B (zh) 2013-02-13 2014-02-13 用于经提升ldpc码的方法、计算机可读存储介质和设备
CN201480008409.6A CN104981978B (zh) 2013-02-13 2014-02-13 使用准循环构造和穿孔以实现高速率、高并行性和低差错本底的ldpc设计
US14/179,871 US20140229788A1 (en) 2013-02-13 2014-02-13 Ldpc design for high rate, high parallelism, and low error floor
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CN105075128A (zh) 2015-11-18
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