SG11202009379VA - Processing method and device for quasi-cyclic low density parity check coding - Google Patents

Processing method and device for quasi-cyclic low density parity check coding

Info

Publication number
SG11202009379VA
SG11202009379VA SG11202009379VA SG11202009379VA SG11202009379VA SG 11202009379V A SG11202009379V A SG 11202009379VA SG 11202009379V A SG11202009379V A SG 11202009379VA SG 11202009379V A SG11202009379V A SG 11202009379VA SG 11202009379V A SG11202009379V A SG 11202009379VA
Authority
SG
Singapore
Prior art keywords
quasi
processing method
low density
parity check
density parity
Prior art date
Application number
SG11202009379VA
Inventor
Liguang Li
Jun Xu
Jin Xu
Original Assignee
Zte Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from CN201710184762.5A external-priority patent/CN108631925B/en
Application filed by Zte Corp filed Critical Zte Corp
Publication of SG11202009379VA publication Critical patent/SG11202009379VA/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
    • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
    • H03M13/1148—Structural properties of the code parity-check or generator matrix
    • H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
SG11202009379VA 2017-03-24 2017-05-24 Processing method and device for quasi-cyclic low density parity check coding SG11202009379VA (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
CN201710184762.5A CN108631925B (en) 2017-03-24 2017-03-24 Quasi-cyclic low-density parity check coding processing method and device
CN2017085398 2017-05-22
PCT/CN2017/085786 WO2018171043A1 (en) 2017-03-24 2017-05-24 Processing method and device for quasi-cyclic low density parity check coding

Publications (1)

Publication Number Publication Date
SG11202009379VA true SG11202009379VA (en) 2020-10-29

Family

ID=63583977

Family Applications (1)

Application Number Title Priority Date Filing Date
SG11202009379VA SG11202009379VA (en) 2017-03-24 2017-05-24 Processing method and device for quasi-cyclic low density parity check coding

Country Status (4)

Country Link
US (2) US11368169B2 (en)
CA (1) CA3094841C (en)
SG (1) SG11202009379VA (en)
WO (1) WO2018171043A1 (en)

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US20210218498A1 (en) * 2020-01-10 2021-07-15 California Institute Of Technology Systems and Methods for Communicating Using Nested Low Density Parity Check Codes
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Also Published As

Publication number Publication date
CA3094841C (en) 2023-05-02
US11368169B2 (en) 2022-06-21
US20210013901A1 (en) 2021-01-14
CA3094841A1 (en) 2018-09-27
US20220337268A1 (en) 2022-10-20
US11843394B2 (en) 2023-12-12
WO2018171043A1 (en) 2018-09-27

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