CN108631925B

CN108631925B - Quasi-cyclic low-density parity check coding processing method and device

Info

Publication number: CN108631925B
Application number: CN201710184762.5A
Authority: CN
Inventors: 李立广; 徐俊; 许进
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2017-03-24
Filing date: 2017-03-24
Publication date: 2022-05-03
Anticipated expiration: 2037-03-24
Also published as: CN115065368A; CN108631925A

Abstract

A method and apparatus for processing quasi-cyclic LDPC coding is disclosed. The quasi-cyclic LDPC coding processing method comprises the following steps: determining a processing strategy of the quasi-cyclic low-density parity check LDPC code according to the data characteristics of the information bit sequence to be coded; and according to the processing strategy, performing quasi-cyclic LDPC coding on the information bit sequence based on the basic matrix and the lifting value. The technical scheme can improve the adaptability and flexibility of the quasi-cyclic LDPC coding.

Description

Quasi-cyclic low-density parity check coding processing method and device

Technical Field

The present invention relates to the field of communications technologies, and in particular, to a method and an apparatus for processing quasi-cyclic Low Density Parity Check (LDPC) codes.

Background

Fig. 1 is a block diagram of a digital communication system according to the related art, in which, as shown in fig. 1, three parts are generally included: a transmitting end, a channel, and a receiving end. The transmitting end can perform channel coding on the information bit sequence to obtain a coded code word, interleave the coded code word, map the interleaved bits into modulation symbols, and then process and transmit the modulation symbols according to the communication channel information. In the channel, the data transmission is distorted due to multipath, motion, etc., which cause a specific channel response, and is further deteriorated due to noise and interference. The receiving end receives the modulation symbol data after passing through the channel, and the modulation symbol data is distorted and needs to be specially processed to restore the original information sequence.

According to the method for coding the information sequence by the sending end, the receiving end can carry out corresponding processing on the received data so as to reliably recover the original information bit sequence. The encoding method must be visible at both the transmitting and receiving ends. Generally, the coding processing method is based on Forward Error Correction (FEC) coding, wherein the FEC coding adds some redundant information to an information sequence. The receiving end can reliably recover the original information sequence by using the redundant information.

At a sending end, code Block segmentation is performed on a transmission Block to be transmitted to obtain a plurality of small transmission blocks, and then FEC encoding is performed on the small transmission blocks, where the transmission Block to be transmitted has a certain Transmission Block Size (TBS) and an encoding rate, and the FEC encoding rate is generally defined as a ratio of the number of bits of an original information bit sequence entering an encoder to the number of bits of an actual transmission bit sequence (or a rate matching output sequence). In a Long Term Evolution (Long Term Evolution, abbreviated as LTE) communication system, the size of a transmission block is flexible, so that various size requirements of transmission data packets of the LTE communication system can be met; the LTE communication system adopts Modulation and Coding Scheme (MCS for short) indexes to indicate different combinations of Modulation orders and Coding rates R; the TBS index is determined by some Control Information, such as Downlink Control Information (DCI) or Channel Quality Indication (CQI), and the size of the actual Information bit sequence is jointly determined according to the number of Resource Blocks (RBs) and the TBS index. The channel type may include a data channel and a control channel, where the data channel generally carries data of a User Equipment (UE), and the control channel carries control information, including control information such as MCS index number, channel information, DCI, CQI, and the like. The bandwidth size generally refers to the spectrum width occupied by the system for allocating data transmission, and the LTE system is divided into bandwidths of 20M, 10M, 5M, and the like. The data transmission direction includes uplink data and downlink data, the uplink data generally refers to data transmitted from the user equipment to the base station, and the downlink data refers to data transmitted from the base station to the user equipment.

Some common FEC coding includes: convolutional codes, Turbo codes, and Low Density Parity Check (LDPC) codes. In the FEC encoding process, FEC encoding is performed on an information sequence with k bits to obtain an FEC encoded codeword with n bits (redundant bits are n-k). The LDPC code is a linear block code that can be defined by a very sparse parity check matrix or bipartite graph, and low-complexity encoding and decoding can be realized by using the sparsity of its check matrix, so that the LDPC code is put to practical use. Various practices and theories prove that the LDPC code is the channel code with the most excellent performance under an Additive White Gaussian Noise (AWGN for short) channel, and the performance is very close to the Shannon limit.

LDPC codes are widely used in ieee802.11ac, ieee802.11ad, ieee802.11aj, ieee802.11e, ieee802.11n, microwave communication, optical fiber communication, and the like. In the parity check matrix of the LDPC code, each row is a parity check code, if a certain index position element value in each row is equal to 1, the bit participates in the parity check code, and if the index position element value is equal to 0, the bit does not participate in the parity check code. Quasi-cyclic LDPC codes (quasi-cyclic LDPC) find application in a variety of communication standards because of their very simple description and their simple decoder structure. The quasi-cyclic LDPC coding can also be called structured LDPC coding, a parity check matrix H of the quasi-cyclic LDPC coding is a matrix of mb × Z rows and nb × Z columns, and the quasi-cyclic LDPC coding is composed of mb × nb sub-matrices, each sub-matrix is different powers of a basic permutation matrix with the size of Z × Z, and the basic permutation matrix is a right cyclic shift (or left cyclic shift 1) 1-bit obtaining matrix of a unit; each sub-matrix may also be considered to be a sub-matrix obtained by right cyclic shifting (or left cyclic shifting) several bits of a size of Z × Z unit matrix. At this time, as long as the cyclic shift value and the size of the sub-matrix are known, a quasi-cyclic LDPC code may be determined, and all shift values corresponding to each sub-matrix form an mb × nb matrix, which may be referred to as a base matrix or a base check matrix or a base pattern (base program or base graph), and the size of the sub-matrix may be referred to as a spreading factor or a lifting value (lift size) or a size of the sub-matrix, which is described herein as a lifting value. The quasi-cyclic LDPC code is also called a structured LDPC code because it is very compact and simple in construction and very advantageous for decoder implementation. According to the definition of the quasi-cyclic LDPC code, the parity check matrix of the quasi-cyclic LDPC code has the following form:

if hb is_ijWhen the value is-1, then

Is an all-zero square matrix of size Z × Z, if hb_ijNot equal to-1, then

Hb equal to the basic permutation matrix P_ijThe power of the next power; in order to describe the cyclic shift of the unit matrix more easily in mathematics, in the basic matrix of the quasi-cyclic LDPC code described above, a basic permutation matrix P with a size Z × Z is defined, and the cyclic shift of the unit matrix, that is, the basic permutation matrix P is performed to the power of the corresponding size, where the basic permutation matrix P is as follows:

by such powers hb_ijEach block matrix can be uniquely identified, if a certain block matrix is an all-zero square matrix, the basic matrix is generally represented by-1 or represented by a null value; and if the cyclic shift s of the unit matrix is obtained, s is equal to s, so all hb_ijA base matrix Hb may be constructed, and the base matrix (or base check matrix) Hb of the LDPC code may be expressed as follows:

therefore, the quasi-cyclic LDPC code can be completely and uniquely determined by the base matrix Hb and the lifting value Z, and thus the base matrix Hb of the quasi-cyclic LDPC code includes 2 elements: the element indicating the full-zero square matrix is generally represented by-1 or null, and the element indicating the shift size of the unit matrix cyclic shift is represented by one integer of 0 to (Z-1). In the base matrix Hb, if there are q non-1 elements (elements indicating the shift size of the unit array cyclic shift) in any row, the row of the row is considered to be q in weight, and similarly, the weight can also be defined as the number of all non-1 elements (elements indicating the shift size of the unit array cyclic shift) in any column in the base matrix Hb. The base matrix includes a plurality of parameters: mb, nb, and kb, where mb is the number of rows in the base matrix (equal to the number of columns in the base matrix), nb is the total number of columns in the base matrix, and kb — nb is the number of system columns in the base matrix.

For example, base matrix Hb (2 rows and 4 columns) is as follows and the boost value z is equal to 4:

the parity check matrix is then:

since the quasi-cyclic LDPC codeword is a systematic code, i.e., systematic bits in the codeword are equal to information bits before encoding, only check bits need to be calculated in the quasi-cyclic LDPC encoding. And performing quasi-cyclic LDPC coding according to the parity check matrix. For example, the parity check matrix H may be described as part 2: h ═ Hs; hp]Hs corresponds to a systematic bit matrix, Hp corresponds to a check bit matrix, and according to the LDPC coding principle, for a quasi-cyclic LDPC codeword C (including a systematic bit Cs and a check bit Cp), a condition H × C is satisfied as 0, that is [ Hs; hp]×[Cs；Cp]0; thus, Hs × Cs ═ Hp × Cp, and then Cp ═ Hp can be derived^-1X Hs x Cs, where '×' in the formula is binary matrix multiplication, (x)^-1Is a binary matrix inversion calculation; the check bits Cp of the quasi-cyclic LDPC codeword can then be calculated, therebyObtaining a quasi-cyclic LDPC codeword C ═ Cs; cp]。

In the quasi-cyclic LDPC code described above, each element position in the base matrix has only 1 shift value or-1 value, which may be referred to as the number of edges of the quasi-cyclic LDPC code being equal to 1, that is, the corresponding non-1 element position in the base matrix has only 1 shift value; for the quasi-cyclic LDPC coding, there is a base matrix with a corresponding number of edges greater than 1, that is, the non-1 element positions in the base matrix contain multiple shift values, that is, for the parity check matrix, the sub-matrix is formed by superimposing cyclic shifts of multiple unit matrices, and at this time, the number of edges of the quasi-cyclic LDPC coding is greater than 1, for example, the base matrix Hb (2 rows and 4 columns) is as follows and the lifting value z is equal to 4, since the non-1 element positions in the base matrix contain 2 shift values at most, the number of edges of the example base matrix is equal to 2, and the number of edges of the base matrix is equal to the maximum number of shift values in the non-1 element positions in the base matrix:

the parity check matrix is then:

in the LDPC encoding process, original information data (i.e., an information bit sequence) to be transmitted is subjected to an encoding process, where the process may include: firstly, dummy bits (known at the transmitting and receiving end of the dummy bits and not required to be transmitted) need to be filled into an information bit sequence, so that the length of the filled bit sequence reaches the systematic bit length of LDPC coding, and if the length of the information bit sequence is equal to the systematic bit length, filling is not needed; secondly, performing quasi-cyclic LDPC coding on the filled information bit sequence to obtain an LDPC coded output sequence; then, carrying out bit selection on the LDPC coded output sequence to obtain a rate matching output sequence, wherein the ratio of the length of the information bit sequence to the length of the rate matching output sequence is the code rate of the rate matching output sequence; and finally, sending the rate matching output sequence. For the receiving end, the decoding process needs to be performed as follows: first, data sent by a sending end is received, which is generally a Log Likelihood Ratio (LLR) sequence (or may be described as a soft sequence or a soft bit information sequence); secondly, performing bit decoding selection (or rate decoding matching) on the received log-likelihood ratio sequence, and assigning the data corresponding to the dummy bit position filled by the sending end to be a larger numerical value (such as infinity), so as to obtain a log-likelihood ratio sequence to be decoded which is as long as the LDPC coding output sequence of the sending end; then, carrying out LDPC decoding on the log-likelihood ratio sequence to be decoded to obtain an LDPC decoding output sequence; finally, removing the dummy bits from the LDPC decoding output sequence to obtain the original data to be received (or the information bit sequence sent by the sending end).

In LDPC coding and decoding, in order to ensure the characteristics of excellent performance, high throughput, high flexibility, low complexity and the like, the parity check matrix of the LDPC code is closely related to the design. Conversely, if the LDPC parity check matrix is designed poorly, its performance will be degraded and complexity and flexibility may be compromised.

Although the quasi-cyclic LDPC codes have been applied to various communication standards, analysis shows that the code rates and code lengths of various standards are relatively limited, i.e., the flexibility is relatively poor, and the codes are relatively difficult to be compatible with various application scenarios, and the complexity caused by different decoding algorithms of decoding designs under different conditions is not necessarily relatively good. For example, in the IEEE802.11ad standard, there are only 1 code length (672) and 4 code rates (1/2, 5/8, 3/4, 13/16); in the IEEE802.11n standard, there are only 3 code lengths (648, 1296, 1944) and 4 code rates (1/2, 2/3, 3/4, 5/6). It can be seen that, since the quasi-cyclic LDPC codes are defined by partial basis matrices, these quasi-cyclic LDPC codes in use have the disadvantage of insufficient flexibility, i.e., flexible variation of encoding code rate and encoding code length. In a new Radio Access Technology (new RAT) system, a channel coding scheme is required to support a flexible code rate code length, that is, the length of supported information reaches at least the granularity as low as that of an LTE system or even lower, and the code rate can be flexibly changed. For example, the new RAT system includes the following application scenarios: enhanced Mobile Broadband (eMBB) scenes, Ultra-Reliable and Low Latency Communications (URLLC) scenes, or large-scale Internet of things (mMTC) scenes. The maximum downlink throughput in the eMBB scene can reach 20Gbps, and the maximum uplink data throughput can reach 10 Gbps; in URLLC, BLER (Block Error Rate) with the lowest reliability reaching 10e-5 and the shortest time delay of uplink and downlink reaching 0.5 millisecond can be supported; and mtc enables the device battery to be used for years without powering down.

However, the adaptability of LDPC codes to various application scenarios is problematic, such as high and low throughput scenarios, large and small coverage requirements, and the requirements of different operating modes. For the adaptability problem of LDPC codes in the related art, no effective solution exists at present.

Disclosure of Invention

The technical problem to be solved by the invention is to provide a method and a device for processing quasi-cyclic LDPC codes, which can improve the adaptability and flexibility of the quasi-cyclic LDPC codes.

The embodiment of the invention provides a quasi-cyclic LDPC coding processing method, which comprises the following steps:

determining a processing strategy of the quasi-cyclic low-density parity check LDPC code according to the data characteristics of the information bit sequence to be coded;

and performing quasi-cyclic LDPC coding and rate matching output on the information bit sequence based on the basic matrix and the lifting value according to the processing strategy.

An embodiment of the present invention further provides a quasi-cyclic LDPC encoding processing apparatus, including:

the processing module is used for determining a processing strategy of the quasi-cyclic low-density parity check LDPC code according to the data characteristics of the information bit sequence to be coded; and according to the processing strategy, performing quasi-cyclic LDPC coding and rate matching output on the information bit sequence based on the basic matrix and the lifting value;

and the storage module is used for storing the basic matrix and the lifting value.

Compared with the prior art, the quasi-cyclic LDPC coding processing method and the device provided by the embodiment of the invention determine the processing strategy of the quasi-cyclic low-density parity check LDPC coding according to the data characteristics of the information bit sequence to be coded; according to the processing strategy, quasi-cyclic LDPC coding and rate matching output are carried out on the information bit sequence based on the basic matrix and the lifting value.

Drawings

Fig. 1 is a block diagram of a digital communication system according to the related art;

FIG. 2 is a flow chart of a method of processing a quasi-cyclic LDPC encoding according to embodiment 1 of the present invention;

FIG. 3 is a schematic diagram of an example 1 of a basic matrix in embodiment 1 of the present invention;

fig. 4 is a schematic diagram of an example 1 of a core matrix check block B in a base matrix in embodiment 1 of the present invention;

FIG. 5 is a schematic diagram of an example 2 of a basic matrix in embodiment 1 of the present invention;

FIG. 6 is a schematic diagram of an example 3 of a basic matrix in embodiment 1 of the present invention;

fig. 7 is a schematic diagram of an example 4 of a basic matrix in the embodiment 2 of the present invention;

fig. 8 is a schematic diagram of an example of a base matrix 5 in the embodiment 2 of the present invention;

fig. 9 is a schematic diagram of an example of a base matrix 6 in embodiment 2 of the present invention;

fig. 10 is a schematic diagram of an example 7 of a basic matrix in the embodiment 2 of the present invention;

fig. 11 is a schematic diagram of an example 8 of a basic matrix in embodiment 2 of the present invention;

fig. 12 is a schematic diagram of an example 9 of a basic matrix in embodiment 2 of the present invention;

FIG. 13 is a diagram of a quasi-cyclic LDPC encoding processing apparatus according to embodiment 3 of the present invention;

FIG. 14 is a schematic diagram of an electronic device for a quasi-cyclic LDPC encoding process according to embodiment 4 of the present invention;

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the embodiments and features of the embodiments in the present application may be arbitrarily combined with each other without conflict.

The quasi-cyclic LDPC coding processing method provided in the embodiments of the present invention may be used in a New Radio Access Technology (New RAT) communication system, and may also be used in an LTE mobile communication system, a future fifth generation mobile communication system, or other wireless wired communication systems.

The data transmission direction is that the base station sends data (downlink transmission service data) to the mobile user (user equipment UE), or the data transmission direction is that the mobile user (user equipment UE) sends data (uplink transmission service data) to the base station.

The mobile user comprises: a mobile device, an access terminal, a user terminal, a subscriber station, a subscriber unit, a mobile station, a remote terminal, a user agent, a user equipment, or some other similar terminology device. The base station includes: an Access Point (AP), a Node B (Node B), a Radio Network Controller (RNC), an Evolved Node B (eNB), a Base Station Controller (BSC), a Base Transceiver Station (BTS), a Base Station (BS), a Transceiver function, a Radio router, a Radio Transceiver, a Basic Service Set (BSs), an Extended Service Set (ESS), a Radio Base Station (RBS), or some other similar terminology device.

Example 1

As shown in fig. 2, embodiment 1 of the present invention provides an example of a method for processing quasi-cyclic LDPC coding, which includes the following steps:

step S210, determining a processing strategy of the quasi-cyclic low-density parity check LDPC coding according to the data characteristics of the information bit sequence to be coded;

and step S220, performing quasi-cyclic LDPC coding and rate matching output on the information bit sequence based on the basic matrix and the lifting value according to the processing strategy.

In this embodiment, the information bit sequence refers to an original information bit sequence entering quasi-cyclic LDPC coding, and the information bit sequence has different data characteristics according to different use conditions (for example, application scenarios, operating modes, transmission directions, user equipment types, and the like) of the information bit sequence.

In this embodiment, the data characteristic of the information bit sequence includes at least one of:

a working mode corresponding to the Information bit sequence, an application scenario corresponding to the Information bit sequence, a link direction corresponding to the Information bit sequence, a user equipment type, length Information of the Information bit sequence, a Modulation and Coding Scheme (MCS) level of the Information bit sequence, an aggregation level of a Control Channel Element (CCE) of the Information bit sequence, a search space corresponding to the Information bit sequence, a scrambling method of the Information bit sequence, a Cyclic Redundancy Check (CRC) format of the Information bit sequence, a Channel type of the Information bit sequence, a Control Information format corresponding to the Information bit sequence, a Channel State Information (CSI) process corresponding to the Information bit sequence, a subframe index number of the Information bit sequence, a Channel length Information of the Information bit sequence, a Coding rate of the Information bit sequence, a Coding rate of the Information sequence, a Coding rate Information of the Information bit sequence, a Coding rate of the Information bit sequence, a Coding rate of the Information bit sequence, a coded Channel of the, A carrier frequency corresponding to the information bit sequence, a release version of the information bit sequence, a coverage of the information bit sequence, a length of a rate matching output sequence obtained by performing quasi-cyclic LDPC coding and bit selection on the information bit sequence, a code rate of the rate matching output sequence, a combination of the code rate of the rate matching output sequence and the length of the information bit sequence, and a Hybrid Automatic Repeat Request (HARQ) data transmission version number of the information bit sequence.

The rate matching output sequence is obtained by aligning an LDPC coding sequence obtained by cyclic LDPC coding and performing bit selection;

in this embodiment, the processing strategy includes determining at least one of the following parameters:

the determining a processing strategy for the quasi-cyclic low density parity check, LDPC, encoding includes determining at least one of:

a core matrix check block structure of the base matrix; orthogonality of the base matrix; a characteristic of the base matrix; a maximum system column number of the base matrix; a maximum number of systematic columns of the quasi-cyclic LDPC encoding; the number of the basis matrices; element correction method of the said basic matrix; the number of edges of the base matrix; the minimum code rate of the basic matrix under the length of the maximum information bit sequence; the minimum code rate of the basic matrix under shortened coding; a value taking method of the lifting value; a granularity dereferencing method of the lifting value; a maximum value of the boost value; performing quasi-cyclic LDPC coding and bit selection on the information bit sequence to obtain the systematic column number of the rate matching output sequence; a check column puncturing method for the rate matching output sequence; an interleaving method of the rate matching output sequence; selecting a starting bit position for a bit of the rate matched output sequence; a maximum information length supported by the quasi-cyclic LDPC encoding; a method for dereferencing the length of information bits supported by the quasi-cyclic LDPC encoding; a method for dereferencing the information bit length granularity supported by the quasi-cyclic LDPC coding; a shortened encoded maximum number of columns of the quasi-cyclic LDPC encoding; a hybrid automatic repeat request HARQ combining mode of the quasi-cyclic LDPC coding; a bit selection starting position of the rate matching output sequence; the HARQ maximum transmission times of the quasi-cyclic LDPC encoding; a number of HARQ transmission versions of the quasi-cyclic LDPC encoding.

In one embodiment, the operating mode includes: an in-band mode, an out-of-band mode, and an independent mode.

In one embodiment, the application scenario of the information bit sequence includes: the method includes the steps of enhancing a mobile broadband eMBB scene, an ultra-reliable low-delay communication URLLC scene and a large-scale Internet of things mMTC scene.

In one embodiment, the link direction of the information bit sequence includes: uplink data and downlink data.

In one embodiment, the length information of the information bit sequence includes: length information greater than a positive integer value K0 and length information less than or equal to a positive integer value K0, where K0 is an integer greater than 128.

In one embodiment, the base matrix Hb is:

a matrix [ A B ] formed by a sub-matrix A and a sub-matrix B is a core matrix of the basic matrix, and the sub-matrix B is a core matrix check block;

the core matrix check block structure is selected from at least 2 structure types: a lower triangular structure, a double-diagonal structure and a quasi-double-diagonal structure;

wherein the matrix of the lower triangular structure comprises the following three features a) -c): a) elements with row index number i and column index number j in the matrix are equal to-1, and j > i; b) all elements on the diagonal in the matrix are non-1 elements; c) at least 1 non-1 element exists in all elements below the diagonal in the matrix;

the matrix of the double diagonal structure comprises the following two features a) -b): a) the head column in the matrix comprises 3 non-1 elements, wherein the head element and the tail element of the head column are both non-1 elements; b) in the matrix, both the element with column index I and row index (I-1) and the element with column index I and row index I are non-1 elements, I ═ 1,2, …, (I0-1), where I0 is the number of rows in the matrix;

the matrix of quasi-dual diagonal structures includes any one of the following features: a) the elements indicated by the row index number (mb0-1) and the column index number 0 in the matrix are non-1 elements, and the submatrix formed by the upper right-hand corner (mb0-1) rows and (mb0-1) columns in the matrix is a dual diagonal structure; b) elements indicated by row index numbers (mb0-1) and column index numbers (mb0-1) in the matrix are non-1 elements, and a submatrix formed by rows (mb0-1) at the upper left corner and columns (mb0-1) in the matrix is of a dual diagonal structure; c) the elements indicated by the row index number 0 and the column index number 0 in the matrix are non-1 elements, and the submatrix formed by the bottom right corner (mb0-1) rows and (mb0-1) columns in the matrix is a dual diagonal structure; where said mb0 is the number of rows of said matrix.

In one embodiment, the base matrix Hb is:

wherein the number of columns of the submatrix D is less than or equal to the number of columns of a core matrix [ A B ] formed by the submatrix A and the submatrix B, the orthogonality of the basic matrix is the orthogonality characteristic of the submatrix D, and the orthogonality of the basic matrix is selected from at least 2 types of the following: orthogonal property, quasi-orthogonal property, non-orthogonal property;

wherein the orthogonal characteristics include: there is no intersection between sets of row indices RowSETi (I ═ 0,1, …, (I-1)), the union of all sets of row indices RowSETi (I ═ 0,1, …, (I-1)) constitutes all row indices of the sub-matrix D, and there are at most 1 non-1 elements in all elements indicated by any one column index in the sub-matrix Di constituted by all rows indicated by sets of row indices RowSETi in the sub-matrix D, where I is a positive integer smaller than the number of rows of the sub-matrix D, and said RowSETi (I ═ 0,1, …, (I-1)) comprises at least 2 elements;

the quasi-orthogonal characteristics include: 2 sets of column indices ColSET0 and ColSET1, the union of ColSET0 and ColSET1 being non-intersecting and the union of ColSET0 and ColSET1 constituting all column indices of said sub-matrix D, the sub-matrix of all columns of the sub-matrix D, indicated by the set of column indices ColSET0, being D0, the sub-matrix of all columns of the sub-matrix D, indicated by the set of column indices ColSET1, being D1, said D1 having said orthogonal property, and D0 not having said orthogonal property;

the non-orthogonal characteristics include: the submatrix D does not have the orthogonal property and the quasi-orthogonal property as described above.

In one embodiment, the maximum number of systematic columns of the base matrix is selected from at least 2 integer values from 2 to 32.

In one embodiment, the maximum systematic number of columns of the base matrix is selected from at least 2 integer values: 4. 6,8, 10, 16,24, 30, 32.

In one embodiment, the number of the base matrices is selected from at least 2 integer values: 1. 2,3 and 4.

In one embodiment, the element modification method of the base matrix is selected from at least 2 of the following methods: a proportional down-rounding method, a mixed complementation method, an adjustment and proportional down-rounding method, a binary bit sequence complementation method, a complementation method to the positive integer power of 2, a complementation method to determine an integer value, an element modification and complementation method, a complementation method to a prime number, an element modification and down-rounding method, a complementation method to a prime number related to a row-column index number; specifically, the method comprises the following steps:

method 1 (proportional down rounding method):

there are one or more basic matrixes with maximum lifting value Zmax, and all basic matrix non-1 element values corresponding to lifting value Z smaller than Zmax are obtained by adopting proportional down rounding operation according to the basic matrix with maximum lifting value Zmax, for example, element P of the basic matrix is obtained by calculating according to the following calculation formula (1-1)_i,j：

Method 2 (hybrid remainder method):

obtaining the element P of the basic matrix by calculation according to the following calculation formula (1-2)_i,j：

Method 3 (adjusted and scaled down rounding method):

calculating and obtaining the element P of the basic matrix according to the following calculation formula_i,j：

Method 4 (binary bit sequence access method):

obtaining the elements P of the basis matrix in the following way_i,j：

Each non-1 element position of the basic matrix is provided with a bit sequence with L bits, all lifting values form an H group lifting value set, if Z belongs to a kth group lifting value set, the element values of the non-1 positions corresponding to the basic matrix of the kth group lifting value set are: selecting k bits from the left, the 2k bits and the 2k-1 bits from the L bit sequences corresponding to the non-1 element positions to form a (k +2) bit sequence, wherein the numerical value corresponding to the (k +2) bit sequence is the element value of the corresponding non-1 element position in the basic matrix corresponding to the lifting value Z;

method 5 (complementation to positive integer power of 2):

for example, the element P of the basic matrix is obtained by calculation according to the following calculation formula_i,j：

Method 6 (modified and complementation method to the positive integer power of 2): calculating and obtaining the element P of the basic matrix according to the following calculation formula_i,j：

Method 7 (findingThe rest method): calculating and obtaining the element P of the basic matrix according to the following calculation formula_i,j：

Method 8 (complementation method for determining integer values): calculating and obtaining the element P of the basic matrix according to the following calculation formula_i,j：

Method 9 (element correction and complementation method): calculating and obtaining the element P of the basic matrix according to the following calculation formula_i,j：

Method 10 (remainder on prime method): calculating and obtaining the element P of the basic matrix according to the following calculation formula_i,j：

P_i,j＝V_i,j mod z_prime

Method 11 (element correction and rounding down method): calculating and obtaining the element P of the basic matrix according to the following calculation formula_i,j：

Method 12 (complementation of prime numbers in relation to row column index):

obtaining the element value of the modified basic matrix by calculating according to the row index number i, the column index number j and the lifting value Z of the basic matrix, for example, obtaining the element P of the basic matrix by calculating according to the following calculation formula (1-12)_i,j：

Wherein, z is_primeIs the largest prime number less than or equal to the boost value Z.

Wherein, V_i,jIs corresponding to Z_maxOf the ith row and the jth column of the base matrix, P_i,jIs the ith row and jth column element value of the base matrix corresponding to Z, Z is the lifting value of the quasi-cyclic LDPC coding, Z_maxIs an integer greater than 0, Z is less than or equal to Z_maxA positive integer of (d);

the t is as follows:

s is such that 2^sThe maximum integer less than or equal to Z;

w is a determined integer value corresponding to the boost value Z; z is_primeIs the largest prime number less than or equal to the boost value Z.

In one embodiment, the minimum code rate of the base matrix at the maximum information bit sequence length is selected from at least 2 real values greater than 0 and less than 1.

In one embodiment, the minimum code rate of the base matrix at the maximum information bit sequence length is selected from at least 2 code rate types: 1/12, 1/8, 1/6, 1/5, 1/4, 1/3, 1/2 and 2/3.

In one embodiment, the minimum code rate of the base matrix under shortened coding is selected from at least 2 real values greater than 0 and less than 1.

In one embodiment, the minimum code rate of the base matrix under shortened coding is selected from at least 2 code rate types: 1/12, 1/8, 1/6, 1/5, 1/4 and 1/3.

In one embodiment, the method of taking the lift value is selected from at least 2 of the following types of methods: a positive integer power of 2 and positive integer multiplication value method, a continuous value method, an interval continuous increase value method, a segmented value method, a value method calculated and finely adjusted by the length of an information bit sequence and the column number of a basic matrix system, and a positive integer power of 2 value method. In particular, the amount of the solvent to be used,

the method comprises the following steps:

the lifting value is a product of a positive integer power d of 2 multiplied by a positive integer c; wherein C is an element in the set of positive integers C and D is an element in the set of non-negative integers D;

the method 2 comprises the following steps:

the lifting value is a continuous integer from Zmin to Zmax;

wherein Zmin and Zmax are integers greater than 0, and Zmax is greater than Zmin;

the method 3 comprises the following steps:

the difference between the adjacent lifting values is equal to the integral power of 2;

wherein all lifting values form a set Zset, the set Zset comprises a plurality of subsets, and the difference values of adjacent lifting values of any size in the subsets are all equal to the non-negative integer power of 2;

the method 4 comprises the following steps:

the lifting value is determined by the length of the information bit sequence and the number of columns of the basic matrix system;

the method 5 comprises the following steps:

the lifting value is determined by the length of the information bit sequence, the number of columns of the basic matrix system and an integer set W;

the method 6 comprises the following steps:

the boost value is equal to a positive integer power of 2.

In an embodiment, in the method 1 for taking the lifting value, the set C and the set D are one of the following pairs: c ═ {4,5,6,7} and D ═ 1,2,3,4,5,6,7 }; c ═ {4,5,6,7} and D ═ 0,1,2,3,4,5,6,7 }; c ═ 3,4,5,6,7,8} and D ═ 0,1,2,3,4,5,6 }; c ═ {4,5,6,7} and D ═ 0,1,2,3,4,5,6,7 }; c ═ {16,20,24,28} and D ═ 0,1,2,3,4,5 }; c ═ {16,20,24,28} and D ═ 0,1,2,3,4 }; c ═ 1,2,3,4,5,6,7 and D ═ 1,2,3,4,5,6, 7; c ═ {1,2,3,4,5,6,7} and D ═ 0,1,2,3,4,5,6,7 };

in an embodiment, in the method 3 for taking the lifting value, the set Zset includes one of the following sets: { {1:1:8}, {9:1:16}, {18:2:32}, {36:4:64}, {72:8:128}, {144:16:256} }, { {1:1:8}, {9:1:16}, {18:2:32}, {36:4:64}, {72:8:128}, {144:16:256}, {288:32:320}, { (1: 1:8}, {9:1:16}, {18:2:32}, {36:4:64}, {72:8:128}, {144:16:256}, {288:32:512}, { (1: 1:8}, {10:2:16}, {20:4:32}, {40:8:64} 128, {80:16:128} and {160:32 } are used as a {1: 8: 16} and {10:2:16} are used as a., {160:32:256}, {320:64:512} }, { {2:2:16}, {20:4:32}, {40:8:64}, {80:16:128}, {160:32:256}, and {320:64:512} };

wherein, in a set { a: b: c }, a is the first element in the set, c is the last element in the set, and b is the interval value between two adjacent elements in the set;

in an embodiment, in the method 4 for taking the lifting value, the lifting value Z is:

wherein K is the length of the information bit sequence, and kb is the number of columns of the basic matrix system;

in an embodiment, in the lifting value taking method 5, the lifting value Z is: z ═ Z_orig+W(Z_orig)；

Wherein the content of the first and second substances,

k is the length of the information bit sequence, kb is the number of columns of the fundamental matrix system, W (Z)_orig) Is the integer set W corresponding to said Z_origOne element value of (a);

in an embodiment, in the lifting value taking method 6, the lifting value is taken from one of the following sets: {2,4,8,16,32,64,128,256,512}, {2,4,8,16,32,64,128,256}, {2,4,8,16,32,64,128}, {2,4,8,16,32,64}, and {2,4,8,16,32 }.

In one embodiment, the granularity of the lift value is a difference between any 2 adjacent lift values in all lift values, and the granularity of the lift value is selected from at least 2 method types: 2, a value method of a non-negative integer power; a fixed positive integer value method; and multiplying the first positive integer set by the second positive integer.

In one embodiment, when the method for taking the granularity of the lifting value adopts the method for taking the granularity of the lifting value raised by the power of 2, the set of the granularity of the lifting value includes one of: {1,2,4,8,16}, {1,2,4,8,16,32,64,128 };

when the method for taking the granularity of the lifting value adopts the fixed positive integer, the fixed positive integer is a positive integer less than or equal to 128.

In one embodiment, the maximum value of the lifting value is selected from at least 2 integer values from 4 to 1024.

In one embodiment, the maximum value of the lifting value is selected from at least 2 integer values: 16. 32,64,128,256, 320,384, 512, 768, 1024.

In one embodiment, the maximum information length supported by the quasi-cyclic LDPC encoding is selected from at least 2 integer values from 128 to 8192.

In one embodiment, the maximum information length supported by the quasi-cyclic LDPC encoding is selected from at least 2 integer values: 256. 512, 768, 1024,2048,4096, 6144, 7680, 8192.

In one embodiment, the information bit length granularity supported by the quasi-cyclic LDPC coding is a difference between any 2 adjacent lengths of all supported information bit lengths, and the information bit length granularity value is selected from at least 2 integer values from 2 to 256.

In one embodiment, the information bit length granularity supported by the quasi-cyclic LDPC coding is selected from at least 2 integer values: 2. 4,8,16,32,64,128, 256.

In one embodiment, the quasi-cyclic LDPC coding has a maximum number of columns for shortened coding of

Where Δ K is the maximum number of bits padded in the quasi-cyclic LDPC encoding, Z is a lifting value, and the maximum number of columns of the shortened encoding is selected from at least 2 integer values from 1 to 24.

In one embodiment, the maximum number of columns of shortened codes of the quasi-cyclic LDPC code is selected from at least 2 integer values: 0. 1,2,3,4,5,6, 8,12, 16, 24.

In one embodiment, the systematic column numbers of the rate-matched output sequences are selected from at least 2 integer values of: 0. 1,2 and 3.

In one embodiment, the HARQ combining scheme of the quasi-cyclic LDPC coding is selected from at least 2 types: soft combining mode, incremental redundancy combining mode, and soft combining and incremental redundancy combining mixed mode.

In one embodiment, the maximum number of HARQ transmissions for the quasi-cyclic LDPC encoding is selected from at least 2 integer values: 1. 2,3,4,5 and 6.

In one embodiment, the number of HARQ transmission versions is selected from at least 2 integer values from 1 to 64.

In one embodiment, the number of HARQ transmission versions is selected from at least 2 integer values: 2. 4, 6,8, 12, 16,24, 32.

In one embodiment, the base matrix is selected from one of Y base matrices, Y being an integer greater than 1;

wherein the Y basis matrices include at least one of the following characteristics:

at least 2 basic matrixes which are the same as the template matrixes exist in the Y basic matrixes;

at least 2 basic matrixes with quasi-identical template matrixes exist in the Y basic matrixes;

at least 2 basic matrixes with quasi-identical matrix elements exist in the Y basic matrixes;

at least 2 basic matrixes nested by the template matrixes exist in the Y basic matrixes;

at least 2 basic matrixes with equal template matrix subsets exist in the Y basic matrixes;

at least 2 basic matrixes with equal basic matrix subsets exist in the Y basic matrixes;

the template matrix is obtained by assigning the positions of non-1 elements in the basic matrix to be 1 and assigning the positions of-1 elements to be 0;

the quasi-identity of the template matrixes means that: the 2 template matrixes are different in a elements, wherein a is an integer which is more than 0 and less than or equal to 10;

the quasi-identity of the matrix elements means that: b elements of the 2 basic matrixes are different, wherein b is an integer which is greater than 0 and less than or equal to 10;

in the 2 basic matrixes nested in the template matrix, the template matrix of the small basic matrix is a sub-matrix of the template matrix of the large basic matrix;

the equal subset of the template matrix means that: one sub-matrix exists in the template matrix of the basic matrix 1 and is equal to one sub-matrix in the template matrix of the basic matrix 2;

the base matrix subsets being equal means that: there is one sub-matrix in the base matrix 1 equal to one sub-matrix in the base matrix 2.

Some description of the basis matrix and lifting values follows:

a base matrix for quasi-cyclic LDPC coding, the elements in the base matrix comprising 2 types: 1) elements indicating an all-zero square matrix, typically represented by-1 or null, here represented by-1; 2) an element indicating a shift size of a unit array cyclic shift, the value of which is an integer value from 0 to Z-1, wherein Z is a lifting value of the quasi-cyclic LDPC encoding. The basic matrix of the quasi-cyclic LDPC coding is in the form of:

wherein, a matrix [ A B ] formed by the submatrix A and the submatrix B is a core matrix (core matrix or kernel matrix) of the basic matrix of the quasi-cyclic LDPC coding, the submatrix A is a core matrix system block, and the submatrix B is a core matrix check block; the submatrix C, the submatrix D, and the submatrix E are 3 submatrices for extending the core matrix to obtain a lower code rate.

In the example of the base matrix shown in fig. 3, submatrix a is 401, submatrix B is 402, submatrix C is 403, submatrix D is 404, and submatrix E is 405. The core matrix check block structure (B) of the basic matrix can be selected from at least 2 of the following structures: lower triangular structure, double diagonal structure, quasi-double diagonal structure.

The lower triangular structure is as follows: the matrix includes 3 properties: 1) elements with row index number i and column index number j in the matrix are both equal to-1 (indicating elements of a full zero square matrix), and column index number j is greater than row index number i; 2) all elements on the diagonal in the matrix are non-1 elements; 3) there are at least 1 non-1 element in all elements below the diagonal in the matrix. The matrix shown in fig. 4(a) is exemplified by a lower triangular structure.

The double diagonal structure is as follows: the matrix includes 2 properties: 1) the head column in the matrix comprises 3 non-1 elements, wherein the head element and the tail element of the head column are both non-1 elements; 2) the 2 elements in the matrix, indicated by a column index I and a row index (I-1) and a row index I, are all non-1 elements, I being 0,1,2, …, (I0-1), where I0 is the number of rows in the matrix. The matrix example shown in fig. 4(b) is a double diagonal structure.

The quasi-dual diagonal structure comprises one of: 1) the elements indicated by the row index number (mb0-1) and the column index number 0 in the matrix are non-1 elements, and the submatrix formed by the upper right-hand corner (mb0-1) rows and (mb0-1) columns in the matrix is a dual diagonal structure; in the example of the matrix structure of mb0 × mb0 ═ 5 × 5 as shown in fig. 4(c), the 4 × 4 sub-matrix in the upper right corner is a dual diagonal structure, and the 4 th row and 0 th column elements are non-1 elements; 2) elements indicated by row index numbers (mb0-1) and column index numbers (mb0-1) in the matrix are non-1 elements, and a submatrix formed by rows (mb0-1) at the upper left corner and columns (mb0-1) in the matrix is of a dual diagonal structure; in an example of a matrix structure of mb0 × mb0 ═ 5 × 5 as shown in fig. 4(d), the upper left 4 × 4 sub-matrix is a dual diagonal structure, and the 4 th row and 4 th column elements are non-1 elements; 3) the elements indicated by the row index number 0 and the column index number 0 in the matrix are non-1 elements, and the submatrix formed by the bottom right corner (mb0-1) rows and (mb0-1) columns in the matrix is a dual diagonal structure; in the example of the matrix structure of mb0 × mb0 ═ 5 × 5 as shown in fig. 4(e), the 4 × 4 sub-matrix in the lower right corner is a dual diagonal structure, and the 0 th row and 0 th column elements are non-1 elements; where said mb0 is the number of rows of said matrix.

The orthogonality of the basic matrix refers to the orthogonality of the sub-matrix D in the basic matrix of the quasi-cyclic LDPC coding described above. The orthogonality of the basis matrix may be selected from at least 2 of: orthogonal characteristics, quasi-orthogonal characteristics, non-orthogonal characteristics, quasi-non-orthogonal characteristics, and the like.

Wherein the orthogonal characteristic is that: there is no intersection between sets of row indices RowSETi (I ═ 0,1, …, (I-1)), a union of all sets of row indices RowSETi (I ═ 0,1, …, (I-1)) constitutes all row indices of the submatrix D, and at most 1 non-1 element (an element indicating a shift size of a cyclic shift of a unit matrix) among all elements indicated by any one column index in the submatrix Di constituted by all rows indicated by the sets of row indices RowSETi in the submatrix D, where I is a positive integer smaller than the number of rows of the submatrix D. All elements in the set of row indices RowSETi are consecutive positive integers, I ═ 0,1, …, (I-1).

In the example of the base matrix shown in fig. 5, the sub-matrix D is shown as 601 in fig. 5, and there are 4 sets of row index numbers in the sub-matrix D: where RowSET0 is {0,1,2}, RowSET1 is {3,4}, RowSET2 is {5,6,7,8}, RowSET3 is {9,10,11,12}, it can be seen that there are at most 1 non-1 element (an element indicating a shift size of a unit matrix cyclic shift) among all elements (3 elements) indicated by any one column index in a submatrix 602(3 rows and 20 columns) composed of all rows indicated by a row index set RowSET0 in a submatrix D (601); similarly, it can be seen that, in the submatrix D (601), which is composed of all rows indicated by the row index set RowSET1, among all elements (2 elements) indicated by any one column index, there are at most 1 non-1 element (element for indicating the shift size of the unit matrix cyclic shift) in the submatrix 603(2 rows and 20 columns) constituted by all rows indicated by the row index set RowSET1, and the submatrixes 604 and 605 also have the same characteristic, the submatrix D has an orthogonal characteristic, and meanwhile, the basic matrix of the legend shown in fig. 5 can be considered to have an orthogonal characteristic, and other basic matrices having the same orthogonal characteristic also belong to the category of the orthogonal characteristic.

Wherein, the quasi-orthogonal characteristic is that: the 2 sets of column indices ColSET0 and ColSET1, the union of ColSET0 and ColSET1 does not intersect and the union of ColSET0 and ColSET1 constitutes all column indices of the submatrix D, the submatrix of the submatrix D constituted by all columns indicated by the set of column indices ColSET0 is D0, the submatrix of the submatrix D constituted by all columns indicated by the set of column indices ColSET1 is D1, the D1 has the orthogonal property as described above, and the D0 does not have the orthogonal property.

In the example of the base matrix shown in fig. 6, the submatrix D (13 rows and 20 columns) is 701 in the figure, ColSET0 is {0,1}, ColSET1 is {2,3,4, …,19}, the submatrix D composed of all columns indicated by the column index set ColSET0 is D0 as 702 in fig. 6, and the submatrix D composed of all columns indicated by the column index set ColSET1 is D1 as 703 in fig. 6, and it can be found that the submatrix D1 has the orthogonal characteristic as described above, and the submatrix D0 does not have the orthogonal characteristic. And other base matrices having the same quasi-orthogonal property also fall within the category of the quasi-orthogonal property. In performing rate matching, the rate matching output sequence obtained by bit selection does not contain systematic bits of F × Z bits corresponding to the column index of the base matrix ColSET2, the ColSET2 being a subset of the ColSET 0. In the example of the basic matrix shown in fig. 6, the ColSET2 ═ {0,1}, i.e., F ═ 2, systematic bits of the first F × Z ═ 2 × Z bits of the quasi-cyclic LDPC mother code codeword are not included in the rate matching output sequence.

Wherein the non-orthogonal characteristic is that: the submatrix D does not have the orthogonal characteristic and the quasi-orthogonal characteristic as described above, such as the submatrix D (801) of the basic matrix example shown in fig. 7.

Wherein the quasi-non-orthogonal characteristic is that: the submatrix D does not have the orthogonal property and the quasi-orthogonal property as described above, and satisfies: the remainders obtained by dividing 2 adjacent non-1 element values on any column in the matrix by positive integers P, which are integers greater than 1, are equal. In the example of the basic matrix shown in fig. 8, the sub-matrix D is 901, and the remainder obtained by dividing 2 adjacent non-1 element values on any column of the sub-matrix D by the positive integer P to 2 is equal, that is, the adjacent 2 adjacent non-1 element values are all equal to even numbers or all equal to odd numbers, such as 2 or more encircled adjacent non-1 elements in fig. 8. Has the advantages that: the design of the quasi-cyclic LDPC decoder is simpler, the problem of address conflict between lines and rows in line parallel decoding or block parallel decoding is solved, and the decoding throughput can be greatly improved.

Wherein the characteristics of the basis matrix can be described as: the basis matrix of the quasi-cyclic LDPC coding can also be described as follows: [ Hb0Hb1], wherein the number of columns of the sub-matrix Hb0 is equal to the number of columns of the core matrix of the base matrix, and the number of rows of the sub-matrix Hb0 is equal to the number of rows of said base matrix. The base matrix characteristic refers to a characteristic of the sub-matrix Hb0, the sub-matrix Hb0 includes: 2 sets of row index numbers RowX and RowY, wherein the RowX and RowY have no intersection and the union of RowX and RowY forms a set formed by all the row index numbers of the sub-matrix Hb 0; the 2 sets of column indices, ColX and ColY, do not intersect and the union of ColX and ColY constitutes the set of all column indices of the submatrix Hb 0.

The base matrix characteristics include at least 2 of: 1) column blocking quasi-congruence property: the remainders obtained by dividing adjacent 2 non-1 elements at any column in the sub-matrix formed by all rows indicated by the row index number set RowX in the sub-matrix Hb0 by the positive integer P0 are equal, the remainders obtained by dividing adjacent 2 non-1 elements at any column in the sub-matrix formed by all rows indicated by the row index number set RowY in the sub-matrix Hb0 by the positive integer P0 are not equal, and the positive integer P0 is an integer greater than 1; 2) line blocking quasi-congruence characteristics: the remainders obtained by dividing adjacent 2 non-1 elements on any column in the sub-matrix formed by all columns indicated by the column index set ColX by the positive integer P1 in the sub-matrix Hb0 are equal, the remainders obtained by dividing adjacent 2 non-1 elements on any column in the sub-matrix formed by all columns indicated by the column index set ColY by the positive integer P1 in the sub-matrix Hb0 are equal, and the positive integer P0 is an integer greater than 1.

The number of the basic matrixes is as follows: the number of the basic matrixes used in the quasi-cyclic LDPC coding process is considered to be different basic matrixes if template matrixes of the basic matrixes are different, wherein the template matrixes are obtained by assigning a non-1 element position to be 1 and assigning a-1 element position to be 0 in the basic matrixes of the quasi-cyclic LDPC coding; and, different row numbers or column numbers of the mother basic matrix used by the quasi-cyclic LDPC coding are also considered as different basic matrices. The number of the basis matrices may be selected from at least 2 of: 2,3,4,5, 6.

The value-taking method (pattern) of the lifting value is as follows: different lifting value ranges. The values pattern of the lifting value include at least 2 of the following values:

the value pattern mode 1 of the lifting value is as follows: multiplication of positive integer powers of 2 by positive integers, e.g. raising Z to c × 2^dWhere C is an element in set C and D is taken from an element in set D. If the set C is {4,5,6,7} and the set D is {0,1,2,3,4,5,6,7}, then the set of lifting values is: {4,5,6,7,8,10,12,14,16,20,24,28,32,40,48,56,64,80,96,112,128,160,192,224,256,320,384,448,512,640,768,896 }; the set C is {4,5,6,7}, and the set D is {1,2,3,4,5,6,7 }; the set C is {4,5,6,7}, and the set D is {1,2,3,4,5,6,7 }; the set C is {3,4,5,6,7,8}, and the set D is {0,1,2,3,4,5,6 };

the value pattern mode 2 of the lifting value is as follows: a continuous value method, {1,2,3,4,5, …, Zmax } or {2,3,4,5, …, Zmax }, wherein Zmax is an integer greater than or equal to 128;

the value pattern mode 3 of the lifting value is as follows: interval successive increase value method, the value of successive increase being a positive integer power of 2, for example {1:1:8,9:1:16,18:2:32,36:4:64,72:8:128,144:16:256,288:32: Zmax }, where Zmax is an integer greater than or equal to 128, where the expression x0: g: x1 refers to taking an integer no greater than the integer x1 starting from the integer x0 with the interval being a positive integer g, and the expression is null if x0 is greater than x 1; and {2:1:8,10:2:16,20:4:32,40:8:64,80:16:128,160:32:256,320:64: Zmax }, wherein Zmax is an integer greater than or equal to 128; and {2:2:8,12:4:32,40:8:64,80:16:128,160:32:256 }.

The value pattern mode 4 of the lifting value is as follows: the sectional value taking method comprises at least 1 of the following lifting value sets: {8,16,24 }; {32,48,64,96 }; {128,192,256 }; {8,16,24 }; {32,48,64,96 };

the value pattern mode 5 of the lifting value is as follows: calculating and finely adjusting a value-taking method according to the length of the information bit sequence and the column number of a basic matrix system, for example, determining the value-taking method according to the length K of the information bit sequence and the column number kb of the basic matrix system, wherein kb is the system column number of the basic matrix of the quasi-cyclic LDPC coding (equal to the total column number nb minus the total row number mb of the basic matrix); the boost value acquisition includes one of the following modes: 1)

the actual code lifting value is Z ═ Z_orig+ Δ Z, Δ Z values depending on Z_origObtaining a value; 2) the actual code lifting value is

The value pattern mode 6 of the lifting value is as follows: the positive integer power of 2 dereferencing method, { 248163264128256512 }.

The value pattern mode 7 of the lifting value is as follows: {256,192,144,108,81,61,46,35,27,21} or {256,156,96,64,40,25,16,10,6 }.

The value pattern mode 8 of the lifting value is as follows: satisfies a x 2^jJ, J being 5 if a is 16 and 4 otherwise, i.e. the lifting value is the set {16,20,24,28}, J being 0,1, 2.

The granularity pattern of the lifting values refers to the interval between all any 2 lifting values with any size in the lifting value set preset and stored by the quasi-cyclic LDPC coding. The granularity pattern of the lifting value can be selected from at least 2 of the following: 1) a value method of interval 2 raised to the power of non-negative integers, for example, the set of the raised values is {2:2:8,12:4:32,40:8:64,80:16:128,160:32:256}, that is, the set of granularity patterns of the raised values is {2,4,8,16,32 }; 2) a value taking method with an interval of a positive integer, wherein if the set of the lifting values is {2:2:256}, the granularity pattern of the lifting values is {2 }; 3) a second positive integer multiple value method with intervals of a first positive integer set, wherein the first positive integer set is G0, and all the second positive integers form a set G1; for example, if the set G0 is a non-negative integer power of 2, the example G0 is {1,2,4}, and the set G0 is {1,4}, then the granularity pattern set of the lifting values is {1,2,4,8,16}, and the lifting value set is {1:1:16,18:2:32,36:4:64,72:8:128,144:16:256 }; in another example, if G0 is {1,2,3}, and the set G1 is {1,4}, the granularity pattern set of the enhancement values is {1,2,3,4,8,16 }.

The maximum value of the boost value may be selected from at least 2 of: 16. 32,64,128,256, 384, 512, 768, and 1024.

The maximum system column number of the basic matrix is equal to the difference between the total column number and the total row number of the basic matrix of the quasi-cyclic LDPC coding, namely kb is nb-mb, kb is the maximum system column number of the basic matrix, nb is the total column number of the basic matrix, and mb is the total row number of the basic matrix. The maximum systematic column number kb of the basis matrix can be selected from at least 2 of: 1) kb is 8; 2) kb is 10; 3) kb is 16; 4) kb is 24; 5) kb is 30; 6) kb is 32.

The maximum system column number of the quasi-cyclic LDPC coding is equal to the maximum system column number of the basic matrix actually used for the quasi-cyclic LDPC coding, for example, the maximum system column number of the original basic matrix is kb, and the system column number of the basic matrix actually used for the quasi-cyclic LDPC coding is smaller than or equal to kb, that is, the basic matrix actually used for the quasi-cyclic LDPC coding is composed of part or all of the system columns and part or all of the check columns of the original basic matrix. The maximum systematic column number of the quasi-cyclic LDPC encoding is selected from at least 2 integer values of 2 to 32; preferably, the maximum systematic column number of the quasi-cyclic LDPC coding may be selected from at least 2 of: 1) 3; 2) 4; 3) 5; 4) 6; 5) 7; 6)8.

The information bit length pattern supported by the quasi-cyclic LDPC coding refers to an information bit sequence length that can be supported by the quasi-cyclic LDPC coding under the condition of carrying out certain padding dummy bits, and the information bit length pattern supported by the quasi-cyclic LDPC coding can be selected from at least 2 of the following: 1) at intervals of a fixed number of bits, e.g. the information bit length pattern, is set { TBS ', TBS' + Δ TBS, TBS '+ 2 × Δ TBS, …, TBSmax }, where TBS' equals 8,16,24, 32 or 40, TBSmax equals 2048,4096, 6144 or 8192, Δ TBS is a fixed positive integer; 2) with respect to the set of {8,16,32,64} in the interval, as the information bit length pattern, the set of { { TBS0, TBS0+8, TBS0+2 × 8, …, TBS0+ L1 × 8}, { TBS0+ L1 × 8+16, TBS0+2 × 16, …, TBS0+ L1 × 8+ L2 × 16}, { TBS0+ L1 × 8+ L2 × 16+32, TBS0+ L1 × 8+ L2 × 16+2 × 32, …, TBS0+ L1 × 8+ L1 × 16+ L1 × 32}, { TBS 1 + L1 × 8+ L1 × 16+ L1 × 32+ 1 × 32, TBS 1 + L1 × 8+ L1 × 1 + L1 × 32, TBS 1 × 1 + L1 × 1, wherein TBS 1 +3, TBS 1 × 1 +1, TBS 1 × 1 +3, TBS 1 × 1, or TBS 1 × 1 is equal to the set of TBS 1 × 1 +1, TBS 1 +1, where TBS 1, TBS 1 × 1 +1 × 1, TBS 1 +1, where. 3. Equal to 2 raised to the positive integer power, the information bit length pattern being the set2, 4,8,16,32,64,128,256,512,1024,2048,4096,8192,16384.

The number of the basic matrixes is the number of the basic matrixes needed to be used in the quasi-cyclic LDPC coding process, and the number of the basic matrixes can be selected from at least 2 of the following types: 1)1 basic matrix; 2)2 basis matrices; 3)3 basis matrices; 4)4 basis matrices.

The maximum information length supported by the quasi-cyclic LDPC coding is a maximum information bit sequence length supported by a quasi-cyclic LDPC coding basis matrix, and is generally equal to an integer value obtained by multiplying a maximum systematic column number of the quasi-cyclic LDPC coding basis matrix by a maximum lifting value, where the maximum information length supported by the quasi-cyclic LDPC coding may be selected from at least 2 of the following: maximum information bit sequence length 1: kmax is 1024; maximum information bit sequence length 2: kmax 2048; maximum information bit sequence length 3: kmax is 4096; maximum information bit sequence length 4: kmax is 6144; maximum information bit sequence length 5: kmax is 8192; maximum information bit sequence length 6: kmax is 512; maximum information bit sequence length 7: kmax 12288; maximum information bit sequence length 8: kmax is 768.

The minimum code rate of the basic matrix under the length of the maximum information bit sequence is the minimum code rate supported by the quasi-cyclic LDPC coding basic matrix under the length of the maximum information bit sequence, and the minimum code rate of the basic matrix under the length of the maximum information bit sequence can be selected from at least 2 of the following types: the minimum code rate is 1: 1/12; the minimum code rate is 2: 1/8; the minimum code rate is 3: 1/6; the minimum code rate is 4: 1/5; the minimum code rate is 5: 1/4; the minimum code rate is 6: 1/3; the minimum code rate is 7: 1/2; the minimum code rate is 8: 2/3.

The systematic column non-transmission pattern of the rate matching output sequence refers to the number of systematic columns corresponding to systematic bit non-transmission in the rate matching process of the quasi-cyclic LDPC code, and the systematic column non-transmission pattern may be selected from at least 2 of the following: the system column does not pass pattern 1: 0; the system column does not pass pattern 2: 1; the system column does not pass pattern 3: 2; the system column does not pass pattern 4: 3.

the shortened coding pattern of the quasi-cyclic LDPC coding refers to the number of at most systematic columns occupied by dummy bits filled in the quasi-cyclic LDPC coding process, and the shortened coding pattern can be selected from at least 2 of the following types: shortening the code pattern 1: 0; shortening the code pattern 2: 1; shortening the code pattern 3: 2; shortening the code pattern 4: 3; shortening the code pattern by 5: 4; shortening the code pattern 6: 5; shortening the code pattern 7: 6; shortening the code pattern 8: 8; shortening the code pattern 9: 12; the code pattern 9:16 is shortened. When the coding is shortened, the quasi-cyclic LDPC coding can obtain a lower code rate, for example, the size of the basic matrix is mb rows and nb columns, the number of system columns is kb-nb, and the code rate is R kb/nb, and if the coding Δ kb column is shortened, the code rate is changed to R' ═ kb- Δ kb)/(nb- Δ kb), that is, the lower code rate can be obtained.

The check column puncturing pattern of the rate matching output sequence refers to: in the quasi-cyclic LDPC coding, in a rate matching process, parity bits generated by a core matrix are rearranged by using Z (code lifting value) bits as a unit, where the rearranged index sequence is the parity column puncturing pattern, and the parity column puncturing pattern may be selected from at least 2 of the following: check column puncturing pattern 1: a set of even-numbered predecessors from 0 to mb '-1 and odd-numbered successors from 0 to mb' -1; check column puncturing pattern 2: a set of odd-numbered first 0 to mb '-1 and even-numbered second 0 to mb' -1; check column puncturing pattern 3: [0,1,2, …, mb' -1 ]; check column puncturing pattern 4: [ mb '-1, mb' -2, … 2,1,0 ]; wherein mb 'is the number of check columns of the core matrix, and mb' is an integer greater than or equal to 3.

The information bit length granularity pattern supported by the quasi-cyclic LDPC coding refers to: the system determines the interval size of the information transmission block sizes of any 2 adjacent numerical values, and the information bit sequence length granularity pattern may be selected from at least 2 of the following: the length of the information bit sequence is granularity pattern 1:2 bits; the length of the information bit sequence is granularity pattern 2:4 bits; the length granularity pattern 3:8 bits of the information bit sequence; the length of the information bit sequence is granularity pattern 4:16 bits; the length of the information bit sequence is granularity pattern 5:32 bits; the length of the information bit sequence is granularity pattern 6:64 bits; information bit sequence length granularity pattern 7:128 bits; the information bit sequence length granularity pattern 8:256 bits. The set of information bit lengths supported by all the quasi-cyclic LDPC codes may be described by a formula or a data table.

The number of edges of the basic matrix is the maximum value of the number of shift values of all element positions in the basic matrix of the quasi-cyclic LDPC coding, and the number of edges of the basic matrix can be selected from at least 2 of the following: the number of edges of the basic matrix is 1: 1; the number of edges of the basic matrix is 2: 2; the number of edges of the basic matrix is 3: 3.

The HARQ combining mode of the quasi-cyclic LDPC coding is a data combining mode adopted by the quasi-cyclic LDPC coding when retransmission data occurs, and the HARQ combining mode may be selected from at least 2 of the following: HARQ combining method 1: a Chase Combining (CC) mode; HARQ combining scheme 2: incremental Redundancy (IR) merging; HARQ combining scheme 3: chase combining is mixed with incremental redundancy combining.

The bit selection starting bit position of the rate matching output sequence is the starting bit position of the quasi-cyclic LDPC coding for bit selection of the retransmission data when the retransmission data occurs, and the bit selection starting bit position of the rate matching output sequence can be selected from at least 2 of the following types: bit selection starting bit position 1 of the rate matching output sequence: is the next cyclic bit position of the last transmitted data tail bit; bit selection starting bit position 2 of the rate matching output sequence: the bit of the rate matching output sequence of the RV-th transmission selects the starting bit position as TXMax, the number P of systematic column untransmissions and the lifting value Z according to the code length L, HARQ of the quasi-cyclic LDPC code, wherein the starting bit position is

Bit selection starting bit position 3 of the rate matching output sequence: the bit selection starting bit position of the rate matching output sequence of the RV-th transmission is related to the number RVnum of transmission versions of the quasi-cyclic LDPC code length L, HARQ, the number P of system column untransmissions and the lifting value Z, for example

The HARQ maximum transmission times of the quasi-cyclic LDPC coding refers to the maximum transmission times (including first transmission and retransmission) of the quasi-cyclic LDPC coding in the data transmission process if a transmission error occurs, and the HARQ maximum transmission times may be selected from at least 2 of the following: the HARQ maximum transmission frequency mode is 1: 2; HARQ maximum transmission times mode 2: 3; the HARQ maximum transmission frequency mode is 3: 4; the HARQ maximum transmission frequency mode is 4:5 times; HARQ maximum transmission mode 5: 1.

The number of the HARQ transmission versions of the quasi-cyclic LDPC coding refers to the number of the transmission versions provided by the quasi-cyclic LDPC coding in a data transmission process if data transmission is wrong, each transmission version number corresponds to a bit selection starting position of transmission data, the number of the transmission versions is an integer which is larger than or equal to the maximum number of the HARQ transmission times of the quasi-cyclic LDPC coding, and when the data transmission is wrong and needs to be retransmitted, one transmission version number and the corresponding bit selection starting position of the transmission data are selected from the multiple transmission versions to carry out rate matching and transmission. The number of HARQ transmission versions may be selected from at least 2 of: number of HARQ transmission versions 1: 2; number of HARQ transmission versions 2: 4; number of HARQ transmission versions 3: 6; number of HARQ transmission versions 4: 8; number of HARQ transmission versions 5: 12; number of HARQ transmission versions 6: 16; number of HARQ transmission versions 7: 24; number of HARQ transmission versions 8: 32; number of HARQ transmission versions 9: 48; HARQ transmission version number 10: 64.

The interleaving pattern of the rate matching output sequence refers to: and aligning interleaving operation of a rate matching output sequence obtained by rate matching after cyclic LDPC coding, wherein the interleaving pattern can be selected from at least 2 of the following: 1. bit rearrangement, i.e. the check bits of the rate-matched output sequence are dispersedly interleaved with the systematic bits, and the check bits are dispersed in the systematic bits, for example, by using a marching list block interleaving method whose depth is related to at least one of the following parameters: the method comprises the steps of improving a value Z, the total column number of a basic matrix, the column number kb of a system, the row number mb of the basic matrix, the information length K, the code rate R and the code length; 2. in the constellation modulation process of retransmission data, bit rearrangement is carried out on the overlapped part of the retransmission data and the last transmission data, so that the low-reliability bit of the overlapped part of the data which is transmitted in the constellation modulation symbol last time is in the high-reliability bit of the constellation modulation symbol in the retransmission at this time, and soft information amplitude fluctuation caused by high-order constellation modulation is compensated; 3. and circularly interleaving the rate matching output sequence by W multiplied by Z bits, wherein Z is a lifting value used by the quasi-cyclic LDPC coding, and W is an integer larger than 0.

Example 2

An embodiment 2 of the present invention provides a method for processing quasi-cyclic LDPC coding, including:

step S310: according to the maximum information length supported by the quasi-cyclic LDPC coding, carrying out code block segmentation on a transmission block before coding to obtain a plurality of information bit sequences, wherein the length of each information bit sequence is not more than the maximum information length;

step S320: adding padding bits at the tail of the plurality of information bit sequences according to the information bit length pattern supported by the quasi-cyclic LDPC coding, so that the length of the plurality of information bit sequences reaches the length in the information bit length pattern supported by the quasi-cyclic LDPC coding, and the added padding bits are minimum;

step S330: selecting a lifting value used by the quasi-cyclic LDPC coding from the value pattern of the lifting value according to the length of the added information bit sequence, and acquiring a basic matrix used by the quasi-cyclic LDPC coding; correcting elements in the basic matrix according to the lifting value to obtain a corrected basic matrix;

step S340: according to the lifting value and the modified basic matrix, performing quasi-cyclic LDPC coding on the added information bit sequence to obtain an LDPC coded output sequence;

step S350: carrying out rate matching interleaving on the LDPC coding output sequence to obtain an interleaved output sequence, and carrying out bit selection on the interleaved output sequence according to a bit selection starting bit position determined by a transmission version number to obtain a rate matching output sequence; the purpose of said rate matching interleaving is to make the order of bit selection continuous;

step S360: selecting an interleaving method according to an interleaving pattern of the rate matching output sequence, and interleaving the rate matching output sequence to obtain an interleaved bit sequence;

step S370: and carrying out constellation symbol modulation on the interleaved bit sequence to obtain a constellation modulation symbol sequence, and sending the constellation modulation symbol sequence.

In one embodiment, the processing strategy for quasi-cyclic LDPC coding may be determined based on a release version of the information bit sequence;

examples of the release versions include different release version numbers in a 3GPP standard protocol, such as release12, release13, release14, release15, release16, release17, release18, release19, and the like, and the same applies when there are more release versions in the future.

In one embodiment, the processing strategy of the quasi-cyclic LDPC encoding may be determined according to an operation mode of the information bit sequence.

Wherein, the working mode at least comprises: an in-band working mode, an out-band working mode, an independent working mode, a mixed working mode and the like, and other working mode definitions are also applicable;

in one embodiment, a processing strategy of the quasi-cyclic LDPC encoding may be determined according to a user equipment type (UE category) of the information bit sequence.

Wherein the user equipment types at least comprise: various user equipment types defined in the LTE system are classified into a plurality of user types according to different transmission peak rates, and other user equipment types are also applicable.

In one embodiment, a processing strategy for quasi-cyclic LDPC coding may be determined based on coverage.

Wherein, the coverage at least comprises: the coverage range is large, the coverage range is small, the coverage range can be a scene where signals are easy to transmit, such as outdoor, and the like, the coverage range is small, such as indoor, and other coverage range definitions are also applicable;

in one embodiment, a processing strategy of the quasi-cyclic LDPC encoding may be determined according to a code rate of the rate-matched output sequence.

Wherein the code rate at least comprises: there are G code rate thresholds, the code rate between which is selected. For example, if G is equal to 1, that is, if there are 1 rate thresholds R0, the rate is divided into a rate smaller than or equal to R0 and a rate larger than R0; if G is equal to 2, that is, there are 2 rate thresholds R0 and R1(R0 is less than R1), the rate is divided into a rate less than or equal to R0, a rate greater than R0 and less than or equal to R1, and a rate greater than R1; other code rate range definitions are equally applicable.

In one embodiment, the processing strategy of the quasi-cyclic LDPC encoding may be determined according to the length (information length) of the information bit sequence.

Wherein the length of the information bit sequence at least comprises: there are G1 information length thresholds, with information length set choices between the G1 information length thresholds. For example, if G1 is equal to 1, that is, if there are 1 information length thresholds K0 of G1, the information lengths are divided into an information length set smaller than or equal to K0 and an information length set larger than K0; if G1 is equal to 2, that is, there are 2 information length thresholds K0 and K1(K0 is less than K1) at G1, the information lengths are divided into an information length set less than or equal to K0, an information length set greater than K0 and less than or equal to K1, and an information length set greater than K1; other information length range definitions are also applicable;

in one embodiment, the processing strategy of the quasi-cyclic LDPC encoding may be determined according to a combination of a code rate of the rate-matched output sequence and a length (code length) of the rate-matched output sequence.

Wherein the code rate at least comprises: there are G code rate thresholds, the code rate between which is selected. For example, if G is equal to 1, that is, if there are 1 rate thresholds R0, the rate is divided into a rate smaller than or equal to R0 and a rate larger than R0; if G is equal to 2, that is, there are 2 rate thresholds R0 and R1(R0 is less than R1), the rate is divided into a rate less than or equal to R0, a rate greater than R0 and less than or equal to R1, and a rate greater than R1; other code rate range definitions are also applicable;

wherein the code length at least comprises: there are G1 length thresholds, a length set selection between the G1 length thresholds. For example, if G1 is equal to 1, that is, if there are 1 length thresholds K0 of G1, the code length is divided into a length set smaller than or equal to K0 and a length set larger than K0; if G1 is equal to 2, that is, there are 2 length thresholds K0 and K1(K0 is less than K1) at G1, the code length is divided into a length set less than or equal to K0, a length set greater than K0 and less than or equal to K1, and a length set greater than K1; other code length range definitions are also applicable;

in one embodiment, a processing strategy of the quasi-cyclic LDPC encoding may be determined according to a combination of a code rate of the rate-matched output sequence and a length (information length) of the information bit sequence.

In one embodiment, the processing strategy of the quasi-cyclic LDPC encoding may be determined according to a control information format of the information bit sequence.

The Control Information format is determined by a system, and includes a Downlink Control Information (DCI) format, for example, including: control information such as a coded modulation scheme (MCS), HARQ retransmission, resource scheduling information, etc.

In one embodiment, the processing strategy of the quasi-Cyclic LDPC coding may be determined according to a Cyclic Redundancy Check (CRC) format of the information bit sequence.

The CRC scrambling format is determined by a system, downlink data or control information is scrambled to improve the robustness of the system, and the system can carry some control information and the like;

in one embodiment, the processing strategy of the quasi-cyclic LDPC coding may be determined according to a search space corresponding to the information bit sequence.

The Search Space refers to a Common Search Space (Common Search Space) and a user equipment-Specific Search Space (UE-Specific Search Space) defined by the LTE system, and may further include other Search Space definitions.

In an embodiment, a processing strategy of the quasi-cyclic LDPC coding may be determined according to a CSI (Channel State Information) process corresponding to the Information bit sequence.

Wherein, the CSI process refers to channel state information defined by the LTE system, and may further include other channel state information definitions, such as definitions in the 5G or NR system;

in one embodiment, a processing strategy for quasi-cyclic LDPC coding may be determined based on a subframe set index number of the information bit sequence.

Wherein the subframe set index number refers to: the method includes dividing a radio frame data into a plurality of subframes (for example, an LTE system includes 10 subframes, each subframe includes 2 slots), and assigning a subframe index to each subframe, where the subframe index is the subframe set index. And the subframe set index may also include subframe set index definitions defined by other systems, such as definitions in a 5G or NR system;

in one embodiment, the processing strategy of the quasi-cyclic LDPC coding may be determined according to a modulation coding MCS level of the information bit sequence.

Wherein, the modulation coding MCS level of the information bit sequence is a level index number, such as 16 levels, 32 levels or 64 levels, used by the communication system to indicate a modulation order and a code rate. And the modulation coding MCS level may also include other system defined modulation coding MCS level definitions, such as those in a 5G or NR system;

in one embodiment, the processing strategy for quasi-cyclic LDPC encoding may be determined based on at least one of: the link direction of the information bit sequence, the aggregation level of a Control Channel Element (CCE) of the information bit sequence and the scrambling mode of the information bit sequence; the channel type of the information bit sequence, the carrier frequency of the information bit sequence, and the HARQ data transmission version number of the information bit sequence.

Wherein the link direction of the information bit sequence comprises: uplink data or downlink data; the uplink data is data transmitted from the user equipment to the base station, and the downlink data is data transmitted from the base station to the user equipment.

The aggregation level of the Control Channel Element (CCE) of the information bit sequence refers to the number of resource elements allocated to the Control signaling, e.g., {1,2,4,8} in the LTE system, and the corresponding definitions in other communication systems, e.g., the 5G system or the NR system, are also applicable.

The scrambling mode of the information bit sequence refers to scrambling the information bit sequence to scramble or randomize the information bit sequence, the scrambling mode can be various, for example, the scrambling mode can be exclusive-or operation with an isometric random sequence, and the random sequence can be various forms.

The channel type of the information bit sequence may include: data channels, control channels, broadcast channels, etc.; or, more specifically, may include: a physical downlink shared channel (PDSCH for carrying downlink user information and higher layer signaling), a physical broadcast channel (PBCH for carrying main system information block information and transmitting information for initial access), a physical multicast channel (PMCH for carrying multimedia/multicast information), a physical control format indicator channel (PCFICH for carrying information of the size of a control region on the subframe), a physical downlink control channel (PDCCH for carrying information of downlink control, such as uplink scheduling instruction, downlink data transmission indication, common control information, etc.), and a physical harq indicator channel (PHICH for carrying ACK/NACK feedback information for terminal uplink data).

The carrier frequency of the information bit sequence refers to a center frequency within a frequency bandwidth carrying the information bit sequence, and generally, a high carrier frequency may use a large bandwidth, and a low carrier frequency may use a small bandwidth.

The HARQ data transmission version number of the information bit sequence is the HARQ version number of the current data transmission obtained in the control information.

In one embodiment, a processing strategy of the quasi-cyclic LDPC coding may be determined according to an application scenario of the information bit sequence.

Wherein the application scenario includes: the Mobile Broadband Communications system includes an enhanced Mobile Broadband (eMBB), a universal resource link control (URLLC) (Ultra-Reliable and Low Latency Communications) scenario, a mass Machine Type Communications (mtc) (large-scale internet of things) scenario, and other application scenario definitions are also applicable.

In one embodiment, the quasi-cyclic LDPC coding includes Y basic matrices, and 1 basic matrix is selected from the Y basic matrices according to the data characteristics representing the information bit sequence to perform the quasi-cyclic LDPC coding to obtain an LDPC coding sequence, where Y is an integer greater than 1.

The Y basis matrices include at least one of the following characteristics:

1) at least 2 basic matrixes with the same template matrix exist in the Y basic matrixes, and the condition that the template matrixes are the same means that: the 2 basic matrixes are M1 and M2, the template matrix of M1 is equal to the template matrix of M2, and at least 1 non-1 element in the 2 basic matrixes has unequal values; the template matrix is a matrix obtained by assigning a non-1 element position in the base matrix to "1" and assigning a-1 element position in the base matrix to "0". The template matrix has the advantages of the same characteristics: the nested characteristic exists between the basic matrixes, so that the structure of the quasi-cyclic LDPC decoder is more uniform, the soft information storage and reading routes are uniform, and the decoder is more compact and simple.

2) At least 2 basic matrixes with quasi-identical template matrixes exist in the Y basic matrixes, wherein the quasi-identical template matrixes are as follows: the 2 template matrices are different in a number of elements, where a is an integer greater than 0 and less than or equal to 10, for example, 2 basic matrices are M3 and M4, the number of rows of M3 is equal to the number of rows of M4, the number of columns of M3 is equal to the number of columns of M4, a SET of row-column index number pairs corresponding to all non-1 elements in M3 is SET3, a SET of row-column index number pairs corresponding to all non-1 elements in M4 is SET4, where a difference between the SET3 and the SET4 is DS3, the number of elements of DS3 is less than or equal to TH3, a difference between the SET4 and the SET3 is DS4, the number of elements of DS4 is less than or equal to TH4, where TH3 and TH4 are positive integers less than 10.

In the example of the base matrix shown in fig. 9, the SET3 formed by the row and column index number pairs corresponding to all non-1 elements of the base matrix (a) (shown in fig. 9 (a)) is { [0,0], [2,0], [0,1], [1,1], [2,1], [0,2], [1,2], [2,2], [0,3], [1,3], [2,3], [0,4], [1,4], [1,5], [2,5], [2,6] }, and the SET4 formed by the row and column index number pairs corresponding to all non-1 elements of the base matrix (b) (shown in fig. 9 (b)) is { [0,0], [1,0], [0,0], [1,1], [0,2], [0,3], [1,3, [2,3], [0,4], [1,4], [1,5], [2,5], [2,6] }, it can be found that the difference SET DS3 of the SET SET3 and the SET SET4 is { [2,1], [1,2] }, and the difference SET DS4 of the SET SET4 and the SET SET3 is { [1,0] }, i.e., the template matrix of the base matrix (a) and the template matrix of the base matrix (b) have 3 elements different, and it can be considered that the 2 base matrices are template matrices quasi-identical.

The template matrix quasi-identical features have the beneficial effects that: the structure of the quasi-cyclic LDPC decoder is more uniform, the soft information storage and reading routes are uniform, and the decoder is more compact and simple; and each basic matrix has partial specificity, so that the performance of the quasi-cyclic LDPC coding can be good under the condition of hardly changing the structure of a decoder or changing the structure very little.

3) At least 2 basic matrixes with quasi-identical matrix elements exist in the Y basic matrixes, wherein the quasi-identical matrix elements refer to: b elements of the 2 basic matrixes are different, wherein b is an integer which is greater than 0 and less than or equal to 10; for example, 2 base matrices are M5 and M6, up to TH5 row-column index number pairs, the elements in the M5 indexed by the row-column index number pairs not being equal to the elements in the M6 indexed by the same row-column index number pairs; the template matrix is a matrix obtained by assigning a non-1 element position in the base matrix to "1" and a-1 element position in the base matrix to "0", and TH5 is a positive integer smaller than 10. The quasi-identical characteristic of the matrix elements has the beneficial effects that: the interleaving network in the quasi-cyclic LDPC decoder can be still uniform, although some elements are different, the influence on the increased complexity is not great, and the decoder is simple and easy to design. In the example of the basis matrix as shown in fig. 10(a) and 10(b), TH5 is 2, where TH5 is 2 row-column index pairs [1,0] and [0,1 ]. Of course, the template matrix may have 2 basic matrices in different cases, and may have the characteristic that the matrix elements are quasi-identical.

4) At least 2 basic matrixes nested by the template matrixes exist in the Y basic matrixes, and the template matrix nesting refers to: of the 2 basic matrices of the template matrix nest, the template matrix of the small basic matrix is a sub-matrix of the template matrix of the large basic matrix, for example, the 2 basic matrices are M7 and M8, the number of rows of M7 is less than the number of rows of M8, the number of columns of M7 is less than the number of columns of M8, and the template matrix of M7 is a sub-matrix of the template matrix of M8. The template matrix is a matrix obtained by assigning a non-1 element position in the base matrix to "1" and assigning a-1 element position in the base matrix to "0". The template matrix subset equal characteristics have the beneficial effects that: under the condition of different basic matrix sizes, the small basic matrix is a subset of the large basic matrix, namely the small basic matrix is nested in the large basic matrix, so that the quasi-cyclic LDPC code decoder has compatibility, the decoding of different basic matrix sizes can be realized by adopting the same decoder, and the decoding is simple and convenient to design. As shown in fig. 11, the basis matrix (a) (shown in fig. 11 (a)) is a sub-matrix of the basis matrix (b) (shown in fig. 11 (b)).

5) At least 2 basic matrixes with equal template matrix subsets exist in the Y basic matrixes, wherein the equal template matrix subsets refer to: there is one sub-matrix in the template matrix of the basic matrix 1 equal to one sub-matrix in the template matrix of the basic matrix 2, for example, 2 basic matrices are M9 and M10, the number of rows of M9 is less than the number of rows of M10, the number of columns of M9 is less than the number of columns of M10, and the basic matrices M9 and M10 both have the following structures:

the submatrix A and the submatrix B form a core matrix of a basic matrix, the submatrix C, the submatrix D1, the submatrix D2 and the submatrix E are all expanded on the basis of the core matrix and support lower code rate, and the template matrix subsets are equal and comprise one of the following characteristics: 1) the core matrix of the M9 template matrix is a sub-matrix of the core matrix of the M10 template matrix; 2) the sub-matrix D1 of the M9 template matrix is one sub-matrix of the sub-matrix D1 of the M10 template matrix; 3) the sub-matrix D2 of the M9 template matrix is one sub-matrix of the sub-matrix D2 of the M10 template matrix. The template matrix is a matrix obtained by assigning a non-1 element position in the base matrix to "1" and assigning a-1 element position in the base matrix to "0". The template matrix subset equal characteristics have the beneficial effects that: the design of the basic matrix is convenient, the optimization is carried out on a unified template, the design of the decoder is also unified, and the required routing networks are consistent.

6) Among the Y basis matrices, there are at least 2 basis matrices with equal basis matrix subsets, that is, the equal basis matrix subsets refer to: the existence of one sub-matrix in the base matrix 1 is equal to one sub-matrix in the base matrix 2, for example, the 2 base matrices have the matrix structure (including the sub-matrix a, the sub-matrix B, the sub-matrix C, the sub-matrix D1, the sub-matrix D2, and the sub-matrix E) as described above, and the equality of the base matrix subsets means: the 2 basic matrices are M11 and M12, the number of rows of M11 is less than the number of rows of M12, the number of columns of M11 is less than the number of columns of M12, and the basic matrix subset is equal to one of the following features: 1) the core matrix of M11 is a sub-matrix of the core matrix of M12; 2) the sub-matrix D1 of M11 is one sub-matrix of the sub-matrix D1 of M12; 3) the sub-matrix D2 of M11 is one sub-matrix of the sub-matrix D2 of M12. The beneficial effects of the equal characteristics of the basic matrix subsets are as follows: partial submatrices in the basic matrix are equal, so that not only is the decoder routing network and the shift network unified, but also the basic matrix element characteristics of the basic matrix are basically consistent, and the performance of the quasi-cyclic LDPC coding is favorably kept good. The sub-matrix D1 may correspond to a sub-matrix formed by system columns that are not transmitted in the rate matching process;

in one embodiment, at least a predetermined percentage of the positions of non-1 elements in the base matrix are the same as the positions of '1' elements in a reference template matrix, which is a sub-matrix of the following template matrices:

in the template matrix, the condition that the element is equal to '1' indicates that the element corresponding to the position in the basic matrix is a non-1 element value, and the condition that the element is equal to '0' indicates that the element corresponding to the position in the basic matrix is a-1 element value. Preferably, the preset ratio is a real number greater than 60% and less than or equal to 100%.

Preferably, the basic matrix is an example of the basic matrix shown in fig. 12, and the preset proportion is equal to 100%.

Example 3

As shown in fig. 13, embodiment 3 of the present invention further provides a quasi-cyclic LDPC encoding processing apparatus, including:

a processing module 1301, configured to determine a processing strategy of a quasi-cyclic low density parity check LDPC code according to a data feature of an information bit sequence to be coded; and according to the processing strategy, performing quasi-cyclic LDPC coding and rate matching output on the information bit sequence based on the basic matrix and the lifting value;

a storage module 1302, configured to store the base matrix and the lifting value.

In one embodiment, the data characteristics include at least one of:

a working mode corresponding to the information bit sequence, an application scenario corresponding to the information bit sequence, a link direction corresponding to the information bit sequence, a user equipment type, length information of the information bit sequence, a Modulation Coding Scheme (MCS) level of the information bit sequence, an aggregation level of a Control Channel Element (CCE) of the information bit sequence, a search space corresponding to the information bit sequence, a scrambling method of the information bit sequence, a Cyclic Redundancy Check (CRC) format of the information bit sequence, a channel type of the information bit sequence, a control information format corresponding to the information bit sequence, a Channel State Information (CSI) process corresponding to the information bit sequence, a subframe index number of the information bit sequence, a carrier frequency corresponding to the information bit sequence, a release version of the information bit sequence, a transmission mode of the information bit sequence, a Modulation Coding Scheme (MCS) level of the information bit sequence, a search space corresponding to the information bit sequence, a scrambling method of the information bit sequence, a transmission method of the information bit sequence, and a method for transmitting a signal, The coverage range of the information bit sequence, the length of a rate matching output sequence obtained by performing quasi-cyclic LDPC coding and bit selection on the information bit sequence, the code rate of the rate matching output sequence, the combination of the code rate of the rate matching output sequence and the length of the information bit sequence, and the HARQ data transmission version number of the information bit sequence.

In one embodiment, the processing module is configured to determine a processing strategy for a quasi-cyclic low density parity check, LDPC, encoding by:

determining at least one of:

In one embodiment, the operating mode includes: an in-band working mode, an out-of-band working mode and an independent working mode;

the application scene comprises the following steps: enhancing a mobile broadband eMBB scene, an ultra-reliable low-delay communication URLLC scene and a large-scale Internet of things mMTC scene;

the link direction includes: an uplink data direction and a downlink data direction.

In one embodiment, the base matrix Hb is:

In one embodiment, the base matrix Hb is:

In one embodiment, the element modification method of the base matrix is selected from at least 2 of the following methods:

the method comprises the following steps: calculating and obtaining the element P of the basic matrix according to the following calculation formula_i,j：

The method 2 comprises the following steps: calculating and obtaining the element P of the basic matrix according to the following calculation formula_i,j：

The method 3 comprises the following steps: calculating and obtaining the element P of the basic matrix according to the following calculation formula_i,j：

The method 4 comprises the following steps: obtaining the elements P of the basis matrix in the following way_i,j：

the method 5 comprises the following steps: calculating and obtaining the element P of the basic matrix according to the following calculation formula_i,j：

The method 6 comprises the following steps: calculating and obtaining the element P of the basic matrix according to the following calculation formula_i,j：

The method 7 comprises the following steps: calculating and obtaining the element P of the basic matrix according to the following calculation formula_i,j：

The method 8 comprises the following steps: calculating and obtaining the element P of the basic matrix according to the following calculation formula_i,j：

The method 9: calculating and obtaining the element P of the basic matrix according to the following calculation formula_i,j：

The method 10 comprises the following steps: calculating and obtaining the element P of the basic matrix according to the following calculation formula_i,j：

P_i,j＝V_i,j mod z_prime

The method 11 comprises the following steps: calculating and obtaining the element P of the basic matrix according to the following calculation formula_i,j：

The method 12 comprises the following steps: calculating and obtaining the element P of the basic matrix according to the following calculation formula_i,j：

the t is as follows:

s is such that 2^sThe maximum integer less than or equal to Z;

In one embodiment, the method for taking the lifting value is selected from at least 2 methods:

the method comprises the following steps:

the method 2 comprises the following steps:

the lifting value is a continuous integer from Zmin to Zmax;

the method 3 comprises the following steps:

the method 4 comprises the following steps:

the method 5 comprises the following steps:

the method 6 comprises the following steps:

the boost value is equal to a positive integer power of 2.

In one embodiment, in the method 1, the set C and the set D are one of the following pairs of sets: c ═ {4,5,6,7} and D ═ 1,2,3,4,5,6,7 }; c ═ {4,5,6,7} and D ═ 0,1,2,3,4,5,6,7 }; c ═ 3,4,5,6,7,8} and D ═ 0,1,2,3,4,5,6 }; c ═ {4,5,6,7} and D ═ 0,1,2,3,4,5,6,7 }; c ═ {16,20,24,28} and D ═ 0,1,2,3,4,5 }; c ═ {16,20,24,28} and D ═ 0,1,2,3,4 }; c ═ 1,2,3,4,5,6,7 and D ═ 1,2,3,4,5,6, 7; c ═ {1,2,3,4,5,6,7} and D ═ 0,1,2,3,4,5,6,7 };

in the method 3, the set Zset includes one of the following sets: { {1:1:8}, {9:1:16}, {18:2:32}, {36:4:64}, {72:8:128}, {144:16:256} }, { {1:1:8}, {9:1:16}, {18:2:32}, {36:4:64}, {72:8:128}, {144:16:256}, {288:32:320}, { (1: 1:8}, {9:1:16}, {18:2:32}, {36:4:64}, {72:8:128}, {144:16:256}, {288:32:512}, { (1: 1:8}, {10:2:16}, {20:4:32}, {40:8:64} 128, {80:16:128} and {160:32 } are used as a {1: 8: 16} and {10:2:16} are used as a., {160:32:256}, {320:64:512} }, { {2:2:16}, {20:4:32}, {40:8:64}, {80:16:128}, {160:32:256}, and {320:64:512} };

in the method 4, the lifting value Z is:

in the method 5, the lifting value Z is: z ═ Z_orig+W(Z_orig)；

Wherein the content of the first and second substances,

in the method 6, the lifting value is taken as one of the following sets: {2,4,8,16,32,64,128,256,512}, {2,4,8,16,32,64,128,256}, {2,4,8,16,32,64,128}, {2,4,8,16,32,64}, and {2,4,8,16,32 }.

Example 4

An embodiment 4 of the present invention provides an electronic device for quasi-cyclic LDPC encoding processing, including: a memory and a processor;

the memory is configured to hold a program for a quasi-cyclic LDPC encoding process that, when read and executed by the processor, performs the following:

The method embodiment provided in embodiment 1 of the present application may be executed in the electronic device provided in embodiment 3. Fig. 14 is a block diagram of a hardware configuration of an electronic device for quasi-cyclic LDPC encoding processing according to embodiment 3 of the present invention. As shown in fig. 14, electronic device 10 may include one or more (only one shown) processors 102 (processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA), and memory 104 for storing data. It will be understood by those skilled in the art that the structure shown in fig. 14 is merely an illustration and is not intended to limit the structure of the electronic device. For example, the electronic device may also include more or fewer components than shown in FIG. 14, or have a different configuration than shown in FIG. 14.

The memory 104 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the quasi-cyclic LDPC encoding processing method in the embodiment of the present invention, and the processor 102 executes various functional applications and data processing by running the software programs and modules stored in the memory 104, so as to implement the above-mentioned method. The memory 104 may include high speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory located remotely from the processor 1402, which may be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

Example 5

Embodiment 5 of the present invention provides a computer-readable storage medium, which stores computer-executable instructions, and when the computer-executable instructions are executed by a processor, the method is implemented.

It will be understood by those of ordinary skill in the art that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between functional modules/units mentioned in the above description does not necessarily correspond to the division of physical units; for example, one physical component may have multiple functions, or one function or step may be performed by several physical components in cooperation. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as is well known to those of ordinary skill in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, Digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can accessed by a computer. In addition, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media as known to those skilled in the art.

It should be noted that the present invention can be embodied in other specific forms, and various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A quasi-cyclic LDPC coding processing method comprises the following steps:

determining one or more characteristics of a quasi-cyclic low density parity check, LDPC, code and a base matrix to perform the quasi-cyclic LDPC coding based on data characteristics of an information bit sequence to be coded,

wherein the one or more characteristics include a maximum number of systematic columns for the quasi-cyclic LDPC encoding;

wherein the maximum systematic number of columns for the quasi-cyclic LDPC encoding is less than or equal to a difference between a total number of columns and a total number of rows of a base matrix for the quasi-cyclic LDPC encoding; and performing the quasi-cyclic LDPC encoding based on the basis of the basis matrix and lifting values in accordance with the one or more characteristics.

2. The method of claim 1, wherein the data characteristics comprise:

a length of the information bit sequence or a modulation coding scheme, MCS, level of the information bit sequence.

3. The method of claim 1 or 2, wherein determining the one or more characteristics for the quasi-cyclic LDPC encoding comprises determining one of:

a maximum system column number of the base matrix; the minimum code rate of the basic matrix under the length of the maximum information bit sequence; a maximum information length supported by the quasi-cyclic LDPC coding.

4. The method of claim 3, wherein a maximum number of systematic columns of the base matrix is selected from at least 2 of the integer values greater than or equal to 2 and less than or equal to 32.

5. The method of claim 3, wherein the minimum code rate of the base matrix is 1/5 or 1/3 at a maximum information bit sequence length.

6. The method of claim 3, wherein a maximum information length supported by the quasi-cyclic LDPC encoding is equal to a product of a maximum number of systematic columns of the base matrix and a maximum lifting value.

7. The method of claim 1, wherein the maximum systematic number of columns for the quasi-cyclic LDPC encoding comprises: 6 and 8.

8. A method for quasi-cyclic low density parity check, LDPC, coding, comprising:

determining the maximum information length supported by the quasi-cyclic LDPC coding, the minimum code rate of a basic matrix under the maximum information bit sequence length and the difference between the total column number and the total row number of the basic matrix based on the length of an information bit sequence to be coded and the Modulation Coding Scheme (MCS) level of the information bit sequence;

performing the quasi-cyclic LDPC encoding based on the difference value, the maximum information length, and a lifting value.

9. The method of claim 8, wherein a maximum information length supported by the quasi-cyclic LDPC encoding is equal to a product of a maximum number of systematic columns of the base matrix and a maximum lifting value.

10. The method of claim 8, wherein the minimum code rate of the base matrix is 1/5 or 1/3 at a maximum information bit sequence length.

11. A quasi-cyclic LDPC encoding processing apparatus comprising:

a processing module configured to:

determining one or more characteristics of a quasi-cyclic low density parity check, LDPC, code and a base matrix to perform the quasi-cyclic LDPC code based on data characteristics of an information bit sequence to be encoded,

wherein the one or more characteristics include a maximum number of systematic columns for the quasi-cyclic LDPC encoding,

wherein the maximum systematic number of columns for the quasi-cyclic LDPC encoding is less than or equal to a difference between a total number of columns and a total number of rows of a base matrix for the quasi-cyclic LDPC encoding; and the number of the first and second groups,

performing the quasi-cyclic LDPC encoding based on the basis of the basis matrix and lifting values in dependence on the one or more characteristics;

12. The quasi-cyclic LDPC encoding processing apparatus of claim 11,

the data characteristics include:

13. The quasi-cyclic LDPC encoding processing apparatus of claim 11 or 12 wherein the processing module is configured to determine the one or more characteristics for the quasi-cyclic LDPC encoding by:

determining one of: a maximum system column number of the base matrix; the minimum code rate of the basic matrix under the length of the maximum information bit sequence; a maximum information length supported by the quasi-cyclic LDPC coding.

14. The quasi-cyclic LDPC encoding processing apparatus of claim 13,

the maximum number of systematic columns of the base matrix is selected from at least 2 of the integer values greater than or equal to 2 and less than or equal to 32.

15. The quasi-cyclic LDPC encoding processing apparatus of claim 13,

the minimum code rate of the basic matrix under the length of the maximum information bit sequence is 1/5 or 1/3.

16. The apparatus of claim 13, wherein a maximum information length supported by the quasi-cyclic LDPC encoding is equal to a product of a maximum systematic column number and a maximum lifting value of the base matrix.

17. The quasi-cyclic LDPC encoding processing apparatus of claim 11,

the maximum systematic column number of the quasi-cyclic LDPC coding comprises: 6 and 8.

18. An apparatus for quasi-cyclic low density parity check, LDPC, encoding comprising a processor and a memory, the memory storing a computer program that, when executed by the processor, causes the apparatus to be configured to:

19. The apparatus of claim 18, wherein the quasi-cyclic LDPC encoding supports an information bit length equal to a product of a maximum number of systematic columns and a maximum lifting value of the base matrix.

20. The apparatus of claim 18, wherein the base matrix has a minimum code rate of 1/5 or 1/3 at a maximum information bit sequence length.