JP2016507200A5 - - Google Patents

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JP2016507200A5
JP2016507200A5 JP2015557232A JP2015557232A JP2016507200A5 JP 2016507200 A5 JP2016507200 A5 JP 2016507200A5 JP 2015557232 A JP2015557232 A JP 2015557232A JP 2015557232 A JP2015557232 A JP 2015557232A JP 2016507200 A5 JP2016507200 A5 JP 2016507200A5
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lifting
group
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matrix
ldpc
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JP5976960B2 (ja
JP2016507200A (ja
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JP2015557232A 2013-02-13 2014-02-13 高並列性、低エラーフロア、および簡単な符号化原理を有するリフトされたｌｄｐｃ符号のための設計 Active JP5976960B2 (ja)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US201361764476P 2013-02-13 2013-02-13
US61/764,476 2013-02-13
US14/179,942 US9306601B2 (en) 2013-02-13 2014-02-13 LDPC design for high parallelism, low error floor, and simple encoding
US14/179,942 2014-02-13
US14/179,871 US20140229788A1 (en) 2013-02-13 2014-02-13 Ldpc design for high rate, high parallelism, and low error floor
US14/179,871 2014-02-13
PCT/US2014/016279 WO2014127140A1 (en) 2013-02-13 2014-02-13 Design for lifted ldpc codes having high parallelism, low error floor, and simple encoding principle

Publications (3)

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JP2016507200A JP2016507200A (ja) 2016-03-07
JP2016507200A5 true JP2016507200A5 (OSRAM) 2016-07-14
JP5976960B2 JP5976960B2 (ja) 2016-08-24

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JP2015557231A Active JP6542132B2 (ja) 2013-02-13 2014-02-13 高レート、高並列性、および低エラーフロアのために、疑似巡回構成を使用し、パンクチャするｌｄｐｃ設計
JP2015557232A Active JP5976960B2 (ja) 2013-02-13 2014-02-13 高並列性、低エラーフロア、および簡単な符号化原理を有するリフトされたｌｄｐｃ符号のための設計

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JP2015557231A Active JP6542132B2 (ja) 2013-02-13 2014-02-13 高レート、高並列性、および低エラーフロアのために、疑似巡回構成を使用し、パンクチャするｌｄｐｃ設計

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US (2) US20140229788A1 (OSRAM)
EP (2) EP2957037A1 (OSRAM)
JP (2) JP6542132B2 (OSRAM)
KR (2) KR102142142B1 (OSRAM)
CN (2) CN104981978B (OSRAM)
BR (1) BR112015019409B1 (OSRAM)
WO (2) WO2014127129A1 (OSRAM)

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