JP2016082211A - コンタクト開口部のエッチングウインドウのためのlcモジュールレイアウト構成 - Google Patents
コンタクト開口部のエッチングウインドウのためのlcモジュールレイアウト構成 Download PDFInfo
- Publication number
- JP2016082211A JP2016082211A JP2015000713A JP2015000713A JP2016082211A JP 2016082211 A JP2016082211 A JP 2016082211A JP 2015000713 A JP2015000713 A JP 2015000713A JP 2015000713 A JP2015000713 A JP 2015000713A JP 2016082211 A JP2016082211 A JP 2016082211A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- numbered
- etching
- module
- pairs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 30
- 238000005530 etching Methods 0.000 claims description 100
- 238000000034 method Methods 0.000 claims description 80
- 239000004020 conductor Substances 0.000 claims description 11
- 239000011810 insulating material Substances 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 3
- -1 SiOC Inorganic materials 0.000 claims description 2
- 229910020177 SiOF Inorganic materials 0.000 claims description 2
- 229910004298 SiO 2 Inorganic materials 0.000 claims 1
- 238000000059 patterning Methods 0.000 abstract 1
- 230000008569 process Effects 0.000 description 43
- 229910052581 Si3N4 Inorganic materials 0.000 description 17
- 230000015654 memory Effects 0.000 description 16
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 16
- 239000000463 material Substances 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 8
- 230000015572 biosynthetic process Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000013459 approach Methods 0.000 description 2
- 230000001627 detrimental effect Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 230000033228 biological regulation Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000014509 gene expression Effects 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000036961 partial effect Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 230000008707 rearrangement Effects 0.000 description 1
- 230000002829 reductive effect Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 230000000007 visual effect Effects 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
- Chemical & Material Sciences (AREA)
- Geometry (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
Abstract
【解決手段】LCモジュールのレイアウト構成は、絶縁層120と導電層125の対130を、その隣接する対の高さが2個の絶縁層/導電層対の厚さ以下だけ異なるように生成する。
【選択図】図9
Description
M=[log2N]
ここで、表記[...]は「より大きいか等しい最小の整数」を表す。工程510において、ランディングパッド位置をP(0)、P(1)、...、P(N−1)として表記してこれらの数値を表の第1行に配列することは都合が良い。
q=b0×20+b1×21+b2×22+...+b4×24
(N−1)×(テーパー角)×(OP厚)
から
2×(テーパー角)×(OP厚)
へ(N−1)/2の割合で削減される。
Claims (15)
- コンタクトパッドと、前記コンタクトパッドとの接続を可能にする層ごとの開口部とを備える複数のLCモジュール
を備える3次元半導体メモリ構造体であって、
前記LCモジュールは複数のレベル上に配置され、各レベルは1対以上の導電材料及び絶縁材料の交互の層の対(OP層対)から形成され、隣接するレベルの表面間の高さの差が2個のOP層対の厚さを超えない、3次元半導体メモリ構造体。 - 各LCモジュールは、奇数番号が付けられているもの又は偶数番号が付けられているものとして指定され、ゼロによって識別される前記LCモジュールは偶数番号が付けられているものとして指定される、請求項1に記載の装置。
- 連続する番号が付けられたLCモジュールの表面間の高さの差が1個のOP層対の厚さである、請求項2に記載の装置。
- ゼロ番号が付けられた前記LCモジュールの表面は最も高い表面であり、最も大きな番号が付けられた前記LCモジュールの表面は、最も低い表面である、請求項2に記載の装置。
- 最も大きな奇数番号を有する前記LCモジュールの表面が最も大きな偶数番号を有する前記LCモジュールの表面と隣接するように、奇数番号が付けられた前記LCモジュールが隣り合わせにグルーピングされるとともに偶数番号が付けられた前記LCモジュールが隣り合わせにグルーピングされる、請求項4に記載の装置。
- 最も小さい奇数番号を有する前記LCモジュールと前記ゼロ番号が付けられた前記LCモジュールとは互いから最も遠く離れて配置される、請求項4に記載の装置。
- 前記構造体は8個以下のLCモジュールを備えるか、又は8を越える個数のLCモジュールを備える、請求項1に記載の装置。
- 3次元半導体メモリのための複数のLCモジュールを形成する方法であって、
基板の上に形成され、基層と、交互の導電層/絶縁層(OP層対)とを含む半導体積層体を準備することと、
複数のエッチング位置を規定することと、
前記半導体積層体に対して一連のエッチングを実行することにより、OP層対表面を前記エッチング位置において露出させて、いずれの隣接する表面の高さの差も2個のOP層対の厚さを超えないようにすることと、
を含む方法。 - 前記導電層表面を、奇数の整数及び偶数の整数に従って番号付けすることと、
奇数の番号が付けられた導電層表面を一緒にグルーピングすることと、
偶数の番号が付けられた導電層表面を一緒にグルーピングすることと、
を更に含み、
前記実行することは、2を底とする、前記複数のエッチング位置の数の大きさの対数を超えない回数のエッチングを実行することを含む、請求項8に記載の方法。 - 前記規定することはランディングパッドの位置を特定することを含む、請求項8に記載の方法。
- 前記規定することはエッチング位置のうちの偶数番号を特定することを含み、該エッチング位置は2の正の整数乗である、請求項8に記載の方法。
- 前記規定することはエッチング位置のうちの奇数番号を特定することを含む、請求項8に記載の方法。
- 3次元半導体メモリアレイの複数のLCモジュールを形成するように構成される絶縁材料と導電材料との交互の層対を備える装置であって、
前記交互の層は別々の表面を形成し、
いずれの隣接する2つの表面も、導電層/絶縁層の2対の厚さを超える量の高さの差がない、装置。 - 対の数が2の正の整数乗である、請求項13に記載の装置。
- 前記導電材料はポリシリコンを含み、前記絶縁材料はSiO2、SiOC、SiOF、及びそれらの組合せから選択される、請求項13に記載の装置。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/515,739 US9478546B2 (en) | 2014-10-16 | 2014-10-16 | LC module layout arrangement for contact opening etch windows |
US14/515,739 | 2014-10-16 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2016082211A true JP2016082211A (ja) | 2016-05-16 |
JP6478638B2 JP6478638B2 (ja) | 2019-03-06 |
Family
ID=55749671
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2015000713A Active JP6478638B2 (ja) | 2014-10-16 | 2015-01-06 | コンタクト開口部のエッチングウインドウのためのlcモジュールレイアウト構成 |
Country Status (5)
Country | Link |
---|---|
US (1) | US9478546B2 (ja) |
JP (1) | JP6478638B2 (ja) |
KR (1) | KR102304460B1 (ja) |
CN (1) | CN105826317B (ja) |
TW (1) | TWI570807B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10559533B2 (en) | 2017-09-07 | 2020-02-11 | Toshiba Memory Corporation | Semiconductor device and method of manufacturing the same |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108630528A (zh) * | 2017-03-23 | 2018-10-09 | 旺宏电子股份有限公司 | 非对称阶梯结构及其制造方法 |
CN107579074B (zh) * | 2017-08-29 | 2018-12-14 | 长江存储科技有限责任公司 | 一种形成多层复合膜的方法及三维存储器件 |
EP3853899A4 (en) * | 2019-01-31 | 2022-05-11 | Yangtze Memory Technologies Co., Ltd. | STAIR FORMATION IN A THREE-DIMENSIONAL MEMORY DEVICE |
KR20200111551A (ko) | 2019-03-19 | 2020-09-29 | 삼성전자주식회사 | 수직형 메모리 장치 |
WO2021127974A1 (en) * | 2019-12-24 | 2021-07-01 | Yangtze Memory Technologies Co., Ltd. | 3d nand memory device and method of forming the same |
CN111492480B (zh) * | 2020-03-23 | 2021-07-09 | 长江存储科技有限责任公司 | 在三维存储器件中的阶梯结构及用于形成其的方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009016400A (ja) * | 2007-06-29 | 2009-01-22 | Toshiba Corp | 積層配線構造体及びその製造方法並びに半導体装置及びその製造方法 |
JP2010034109A (ja) * | 2008-07-25 | 2010-02-12 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2010192589A (ja) * | 2009-02-17 | 2010-09-02 | Toshiba Corp | 不揮発性半導体記憶装置、及びその製造方法 |
JP2011142276A (ja) * | 2010-01-08 | 2011-07-21 | Toshiba Corp | 不揮発性半導体記憶装置、及びその製造方法 |
US8227897B2 (en) * | 2009-03-03 | 2012-07-24 | Samsung Electronics Co., Ltd. | Integrated circuit resistive devices including multiple interconnected resistance layers |
JP2013187335A (ja) * | 2012-03-07 | 2013-09-19 | Toshiba Corp | 半導体装置及びその製造方法 |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008078404A (ja) * | 2006-09-21 | 2008-04-03 | Toshiba Corp | 半導体メモリ及びその製造方法 |
US7910973B2 (en) * | 2008-03-17 | 2011-03-22 | Kabushiki Kaisha Toshiba | Semiconductor storage device |
JP5305980B2 (ja) * | 2009-02-25 | 2013-10-02 | 株式会社東芝 | 不揮発性半導体記憶装置、及びその製造方法 |
JP2011003833A (ja) * | 2009-06-22 | 2011-01-06 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
US8482051B2 (en) * | 2010-01-11 | 2013-07-09 | Hynix Semiconductor Inc. | 3D nonvolatile memory device including a plurality of channel contacts coupled to a plurality of channel layers and a plurality of section lines coupled to the plurality of channel contacts and method for fabricating the same |
JP5394270B2 (ja) * | 2010-01-25 | 2014-01-22 | 株式会社東芝 | 不揮発性半導体記憶装置及びその製造方法 |
KR101738103B1 (ko) * | 2010-09-10 | 2017-05-22 | 삼성전자주식회사 | 3차원 반도체 기억 소자 |
KR101721117B1 (ko) * | 2011-03-15 | 2017-03-29 | 삼성전자 주식회사 | 반도체 소자의 제조 방법 |
KR101990904B1 (ko) * | 2012-07-17 | 2019-06-19 | 삼성전자주식회사 | 수직형 반도체 소자 |
KR20140075340A (ko) * | 2012-12-11 | 2014-06-19 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 제조 방법 |
KR102046504B1 (ko) * | 2013-01-17 | 2019-11-19 | 삼성전자주식회사 | 수직형 반도체 소자의 패드 구조물 및 배선 구조물 |
-
2014
- 2014-10-16 US US14/515,739 patent/US9478546B2/en active Active
- 2014-12-17 KR KR1020140182158A patent/KR102304460B1/ko active IP Right Grant
- 2014-12-26 TW TW103145873A patent/TWI570807B/zh active
-
2015
- 2015-01-05 CN CN201510001701.1A patent/CN105826317B/zh active Active
- 2015-01-06 JP JP2015000713A patent/JP6478638B2/ja active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009016400A (ja) * | 2007-06-29 | 2009-01-22 | Toshiba Corp | 積層配線構造体及びその製造方法並びに半導体装置及びその製造方法 |
JP2010034109A (ja) * | 2008-07-25 | 2010-02-12 | Toshiba Corp | 不揮発性半導体記憶装置 |
JP2010192589A (ja) * | 2009-02-17 | 2010-09-02 | Toshiba Corp | 不揮発性半導体記憶装置、及びその製造方法 |
US8227897B2 (en) * | 2009-03-03 | 2012-07-24 | Samsung Electronics Co., Ltd. | Integrated circuit resistive devices including multiple interconnected resistance layers |
JP2011142276A (ja) * | 2010-01-08 | 2011-07-21 | Toshiba Corp | 不揮発性半導体記憶装置、及びその製造方法 |
JP2013187335A (ja) * | 2012-03-07 | 2013-09-19 | Toshiba Corp | 半導体装置及びその製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10559533B2 (en) | 2017-09-07 | 2020-02-11 | Toshiba Memory Corporation | Semiconductor device and method of manufacturing the same |
Also Published As
Publication number | Publication date |
---|---|
US20160111429A1 (en) | 2016-04-21 |
CN105826317B (zh) | 2019-04-23 |
US9478546B2 (en) | 2016-10-25 |
JP6478638B2 (ja) | 2019-03-06 |
KR20160044992A (ko) | 2016-04-26 |
KR102304460B1 (ko) | 2021-09-24 |
TWI570807B (zh) | 2017-02-11 |
TW201626457A (zh) | 2016-07-16 |
CN105826317A (zh) | 2016-08-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2016082211A (ja) | コンタクト開口部のエッチングウインドウのためのlcモジュールレイアウト構成 | |
US9312204B2 (en) | Methods of forming parallel wires of different metal materials through double patterning and fill techniques | |
US9472422B2 (en) | Semiconductor device structure and manufacturing methods | |
US20200258895A1 (en) | 3-dimensional junction semiconductor memory device and fabrication method thereof | |
US9786551B2 (en) | Trench structure for high performance interconnection lines of different resistivity and method of making same | |
EP3240028B1 (en) | Contact pad structure and method for fabricating the same | |
TWI660424B (zh) | 在積體電路中形成ana區域之方法 | |
JP2012244180A5 (ja) | ||
WO2019100899A1 (en) | Method and structure for cutting dense line patterns using self-aligned double patterning | |
JP6814377B2 (ja) | ビア対グリッドのパターニングにおけるオーバレイエラーを減少する方法 | |
US20190157082A1 (en) | Method and structure for cutting dense line patterns using self-aligned double patterning | |
KR101710274B1 (ko) | 반도체 장치의 제조 방법, 및 패턴 생성 프로그램을 저장한 컴퓨터 판독 가능한 불휘발성 기억 매체 | |
US9508645B1 (en) | Contact pad structure | |
US9607885B2 (en) | Semiconductor device and fabrication method | |
KR20110013701A (ko) | 반도체 소자 및 그 제조 방법 | |
US20190108943A1 (en) | High voltage capacitors and methods of manufacturing the same | |
US8722535B2 (en) | Pattern forming method, mold and data processing method | |
TWI741367B (zh) | 用於3d互連件的同時金屬圖案化 | |
TW201428938A (zh) | 三維堆疊半導體裝置及其製造方法 | |
JP2006024831A (ja) | 半導体装置および半導体装置の製造方法 | |
TW201838157A (zh) | 多層元件的邊緣結構及其製造方法 | |
JP2005259986A (ja) | 半導体装置及びその製造方法 | |
JP2014053360A (ja) | 半導体装置及びその製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20170714 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20180724 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20181023 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20190108 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20190205 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 6478638 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |