JP2016076692A - 半導体装置およびその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 239000010409 thin film Substances 0.000 claims abstract description 207
- 239000000758 substrate Substances 0.000 claims abstract description 73
- 239000010408 film Substances 0.000 claims description 213
- 239000003963 antioxidant agent Substances 0.000 claims description 91
- 230000003078 antioxidant effect Effects 0.000 claims description 91
- 239000002184 metal Substances 0.000 claims description 24
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 238000000034 method Methods 0.000 claims description 17
- 238000000059 patterning Methods 0.000 claims description 11
- 230000003647 oxidation Effects 0.000 abstract description 6
- 238000007254 oxidation reaction Methods 0.000 abstract description 6
- 230000001681 protective effect Effects 0.000 description 10
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 9
- 150000004767 nitrides Chemical class 0.000 description 9
- 230000003064 anti-oxidating effect Effects 0.000 description 8
- 238000000206 photolithography Methods 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000006185 dispersion Substances 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 229910019974 CrSi Inorganic materials 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229910018182 Al—Cu Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000035699 permeability Effects 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 238000009966 trimming Methods 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01C—RESISTORS
- H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
- H01C7/006—Thin film resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5228—Resistive arrangements or effects of, or between, wiring layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/564—Details not otherwise provided for, e.g. protection against moisture
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
- H01L27/016—Thin-film circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0802—Resistors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/20—Resistors
- H01L28/24—Resistors with an active material comprising a refractory, transition or noble metal, metal compound or metal alloy, e.g. silicides, oxides, nitrides
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
本発明の第1実施形態について図面を参照しつつ説明する。図1に示されるように、半導体装置は、シリコン基板等で構成される基板10を有し、当該基板10には図示しないダイオードやトランジスタ等の半導体素子が形成されている。そして、基板10の一面10a上には、酸化膜20を介して内部に薄膜抵抗体62を有する多層配線層30が配置されている。
本発明の第2実施形態について説明する。本実施形態は、第1実施形態に対して複数の薄膜抵抗体62を形成すると共に、複数の薄膜抵抗体62を用いてペア抵抗を構成したものである。本実施形態のその他の部分に関しては第1実施形態と同様であるため、ここでは説明を省略する。
本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。
10a 一面
40 第1配線層
50 絶縁膜
61 下方酸化防止膜
62 薄膜抵抗体
63 上方酸化防止膜
80 第2配線層
100 絶縁膜
Claims (6)
- 一面(10a)を有する基板(10)と、
前記基板の一面の上方に形成された第1配線層(40)と、
前記第1配線層を覆う絶縁膜(50)と、
前記絶縁膜上に形成された下方酸化防止膜(61、121〜128)と、
前記下方酸化防止膜上に形成された薄膜抵抗体(62、111〜118)と、
前記薄膜抵抗体上に形成された上方酸化防止膜(63、131〜138)と、
前記下方酸化防止膜、前記薄膜抵抗体、前記上方酸化防止膜を覆う絶縁膜(70)と、
前記下方酸化防止膜、前記薄膜抵抗体、前記上方酸化防止膜を覆う前記絶縁膜上に形成された第2配線層(80)と、
前記第2配線層を覆う絶縁膜(100)と、を備え、
前記基板の一面に対する法線方向から視たとき、前記第1配線層は、前記薄膜抵抗体の端部と重複する部分を有していることを特徴とする半導体装置。 - 前記基板の一面に対する法線方向から視たとき、前記第2配線層は、それぞれ前記薄膜抵抗体の端部と重複する部分を有していることを特徴とする請求項1に記載の半導体装置。
- 前記薄膜抵抗体(111〜118)は、複数形成され、所定電圧を分圧するペア抵抗を構成していることを特徴とする請求項1または2に記載の半導体装置。
- 前記基板の一面に対する法線方向から視たとき、前記ペア抵抗を構成する前記薄膜抵抗体と前記第1配線層との重複率が互いに等しくされていることを特徴とする請求項3に記載の半導体装置。
- 複数の前記薄膜抵抗体は、前記基板の面方向における一方向に沿って順に配置されており、
前記ペア抵抗は、複数の前記薄膜抵抗体のうちの前記一方向における両端部に位置する前記薄膜抵抗体の内側に位置する前記薄膜抵抗体を用いて構成されていることを特徴とする請求項3または4に記載の半導体装置。 - 一面(10a)を有する基板(10)と、
前記基板の一面の上方に形成された第1配線層(40)と、
前記第1配線層を覆う絶縁膜(50)と、
前記絶縁膜上に形成された下方酸化防止膜(61、121〜128)と、
前記下方酸化防止膜上に形成された薄膜抵抗体(62、111〜118)と、
前記薄膜抵抗体上に形成された上方酸化防止膜(63、131〜138)と、
前記下方酸化防止膜、前記薄膜抵抗体、前記上方酸化防止膜を覆う絶縁膜(70)と、
前記下方酸化防止膜、前記薄膜抵抗体、前記上方酸化防止膜を覆う前記絶縁膜上に形成された第2配線層(80)と、
前記第2配線層を覆う絶縁膜(100)と、を備え、
前記基板の一面に対する法線方向から視たとき、前記第1配線層は、前記薄膜抵抗体の端部と重複する部分を有している半導体装置の製造方法において、
前記基板を用意する工程と、
前記基板上に前記第1配線層を構成する金属膜(40a)を成膜する工程と、
前記金属膜をパターニングして前記第1配線層を形成する工程と、
前記第1配線層を覆う前記絶縁膜を形成する工程と、
前記第1配線を覆う前記絶縁膜上に前記下方酸化防止膜を構成する第1酸化防止膜(61a)を成膜する工程と、
前記第1酸化防止膜上に前記薄膜抵抗体を構成する金属膜(62a)を成膜する工程と、
前記金属膜上に前記上方酸化防止膜を構成する第2酸化防止膜(63a)を成膜する工程と、
前記第1酸化防止膜、前記金属膜、前記第2酸化防止膜をパターニングすることにより、前記下方酸化防止膜、前記薄膜抵抗体、前記上方酸化防止膜を形成する工程と、
前記下方酸化防止膜、前記薄膜抵抗体、前記上方酸化防止膜を覆う前記絶縁膜を成膜する工程と、
前記下方酸化防止膜、前記薄膜抵抗体、前記上方酸化防止膜を覆う前記絶縁膜上に前記第2配線層を構成する金属膜(80a)を成膜する工程と、
前記金属膜をパターニングして前記第2配線層を形成する工程と、を行い、
前記第1配線層を形成する工程、および前記下方酸化防止膜、前記薄膜抵抗体、前記上方酸化防止膜を形成する工程では、前記基板の一面に対する法線方向から視たとき、前記第1配線層を前記薄膜抵抗体の端部と重複する部分を有するように形成することを特徴とする半導体装置の製造方法。
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PCT/JP2015/005036 WO2016056212A1 (ja) | 2014-10-07 | 2015-10-02 | 半導体装置およびその製造方法 |
US15/502,244 US10854543B2 (en) | 2014-10-07 | 2015-10-02 | Semiconductor device and manufacturing method therefor |
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JP2018107171A (ja) * | 2016-12-22 | 2018-07-05 | 株式会社デンソー | 半導体装置およびその製造方法 |
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KR102460719B1 (ko) | 2018-07-20 | 2022-10-31 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
US20230197320A1 (en) * | 2021-12-17 | 2023-06-22 | Globalfoundries Singapore Pte. Ltd. | Heat dissipating structures |
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JPH0316164A (ja) * | 1988-11-22 | 1991-01-24 | Seiko Epson Corp | 半導体装置 |
JPH11145388A (ja) * | 1997-11-11 | 1999-05-28 | Nec Corp | 半導体装置とその抵抗配置方法 |
JP2003243522A (ja) * | 2002-02-20 | 2003-08-29 | Mitsubishi Electric Corp | 抵抗素子を使用した半導体装置 |
JP2009302082A (ja) * | 2008-06-10 | 2009-12-24 | Hitachi Ltd | 半導体装置およびその製造方法 |
Family Cites Families (9)
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US5428242A (en) * | 1988-11-22 | 1995-06-27 | Seiko Epson Corporation | Semiconductor devices with shielding for resistance elements |
JP2004039925A (ja) | 2002-07-04 | 2004-02-05 | Denso Corp | 半導体装置の製造方法 |
US6789871B2 (en) * | 2002-12-27 | 2004-09-14 | Lexmark International, Inc. | Reduced size inkjet printhead heater chip having integral voltage regulator and regulating capacitors |
JP2005259802A (ja) | 2004-03-09 | 2005-09-22 | Denso Corp | 半導体装置 |
US7176781B2 (en) * | 2004-09-29 | 2007-02-13 | Agere Systems Inc | Structure and method for adjusting integrated circuit resistor value |
US7403094B2 (en) * | 2005-04-11 | 2008-07-22 | Texas Instruments Incorporated | Thin film resistor and dummy fill structure and method to improve stability and reduce self-heating |
JP2011061005A (ja) | 2009-09-10 | 2011-03-24 | Sony Corp | 電子デバイス |
JP2011146520A (ja) | 2010-01-14 | 2011-07-28 | Sanyo Electric Co Ltd | 半導体装置 |
JP5824330B2 (ja) | 2011-11-07 | 2015-11-25 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
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- 2015-09-08 JP JP2015176741A patent/JP6519417B2/ja active Active
- 2015-10-02 US US15/502,244 patent/US10854543B2/en active Active
Patent Citations (4)
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JPH0316164A (ja) * | 1988-11-22 | 1991-01-24 | Seiko Epson Corp | 半導体装置 |
JPH11145388A (ja) * | 1997-11-11 | 1999-05-28 | Nec Corp | 半導体装置とその抵抗配置方法 |
JP2003243522A (ja) * | 2002-02-20 | 2003-08-29 | Mitsubishi Electric Corp | 抵抗素子を使用した半導体装置 |
JP2009302082A (ja) * | 2008-06-10 | 2009-12-24 | Hitachi Ltd | 半導体装置およびその製造方法 |
Cited By (1)
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JP2018107171A (ja) * | 2016-12-22 | 2018-07-05 | 株式会社デンソー | 半導体装置およびその製造方法 |
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