JP2016063127A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2016063127A JP2016063127A JP2014191224A JP2014191224A JP2016063127A JP 2016063127 A JP2016063127 A JP 2016063127A JP 2014191224 A JP2014191224 A JP 2014191224A JP 2014191224 A JP2014191224 A JP 2014191224A JP 2016063127 A JP2016063127 A JP 2016063127A
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Abstract
Description
本願において、実施の態様の記載は、必要に応じて、便宜上複数のセクション等に分けて記載するが、特にそうでない旨明示した場合を除き、これらは相互に独立別個のものではなく、記載の前後を問わず、単一の例の各部分、一方が他方の一部詳細または一部または全部の変形例等である。また、原則として、同様の部分は繰り返しの説明を省略する。また、実施の態様における各構成要素は、特にそうでない旨明示した場合、理論的にその数に限定される場合および文脈から明らかにそうでない場合を除き、必須のものではない。
<半導体装置>
本実施の形態は、BGA(Ball Grid Array)型の半導体装置に適用したものであり、図1はこのBGA型の半導体装置の上面側の内部構造を示す平面図、図2は図1のA−A線に沿った断面図である。
本実施の形態2は、上記実施の形態1の変形例に対応している。
チップ搭載面、前記チップ搭載面とは反対側の実装面、前記チップ搭載面上に形成された複数の第1電極パッドおよび複数の第2電極パッド、前記実装面上に形成された複数の外部電極端子を有する配線基板と、
前記配線基板の前記チップ搭載面上に配置され、第1主面、前記第1主面とは反対側の第1裏面、前記第1主面上に形成された複数の第1ボンディングパッドを有する第1半導体チップと、
前記配線基板上の前記複数の第1電極パッドのそれぞれと前記第1半導体チップの前記第1ボンディングパッドのそれぞれを接続する複数の第1ワイヤと、
前記第1半導体チップの前記第1主面上に配置され、第1上面、前記第1上面とは反対側の第1下面を有する第1スペーサと、
前記第1スペーサの前記第1上面上に配置された第1ヒートスラグと、
前記配線基板の前記チップ搭載面上であって、前記第1半導体チップとは異なる領域に配置され、第2上面と、前記第2上面と反対側の第2下面とを有する第2スペーサと、
前記第2スペーサの前記第2上面上に配置され、第2主面、前記第2主面とは反対側の第2裏面、前記第2主面上に形成された複数の第2ボンディングパッドを有する第2半導体チップと、
前記配線基板上の前記複数の第2電極パッドのそれぞれと前記第2半導体チップの前記第2ボンディングパッドのそれぞれを接続する複数の第2ワイヤと、
前記第2半導体チップの前記第2主面上に配置された第2ヒートスラグと、
前記配線基板の前記チップ搭載面、前記第1半導体チップ、前記第2半導体チップ、前記複数の第1ワイヤ、前記第2ワイヤ、前記第1スペーサ、前記第2スペーサ、前記第1ヒートスラグおよび前記第2ヒートスラグを覆う封止体と、
を有し、
前記第2ヒートスラグと前記第2半導体チップの前記第2主面との間には前記封止体が介在し、
前記配線基板の前記チップ搭載面から前記第1ヒートスラグまでの第1距離は、前記配線基板の前記チップ搭載面から前記第2ヒートスラグまでの第2距離よりも大きい、半導体装置。
4 ボンディングパッド
6 ワイヤ
8 スペーサ
9 ヒートスラグ
10 配線基板
11a チップ搭載面
12 電極パッド
23 封止体
SD 半導体装置
Claims (20)
- チップ搭載面、前記チップ搭載面とは反対側の実装面、前記チップ搭載面上に形成された複数の電極パッド、および、前記実装面上に形成された複数の外部電極端子を有する配線基板と、
前記配線基板の前記チップ搭載面上に配置され、主面、前記主面とは反対側の裏面、および、前記主面上に形成された複数のボンディングパッドを有する半導体チップと、
前記配線基板上の前記複数の電極パッドのそれぞれと前記半導体チップの前記ボンディングパッドのそれぞれを接続する複数のワイヤと、
前記配線基板の前記チップ搭載面と前記半導体チップの前記裏面の間に設置され、前記半導体チップの側に上面、前記配線基板の側に下面を有する第1スペーサと、
前記半導体チップの前記主面上に配置されたヒートスラグと、
前記配線基板の前記チップ搭載面、前記半導体チップ、前記複数のワイヤ、前記第1スペーサ、および前記ヒートスラグを覆う封止体と、
を有し、
前記半導体チップの前記主面と前記ヒートスラグとの間には前記封止体が介在する、半導体装置。 - 請求項1に記載の半導体装置において、
平面視において、前記ヒートスラグは、前記半導体チップの前記主面を完全に覆っている、半導体装置。 - 請求項1に記載の半導体装置において、
前記半導体チップは前記第1スペーサの前記上面の中央部に配置され、前記第1スペーサの前記上面の面積は前記半導体チップの前記主面の面積よりも大きい、半導体装置。 - 請求項3に記載の半導体装置において、
前記半導体チップおよび前記第1スペーサは、シリコンからなる、半導体装置。 - 請求項1に記載の半導体装置において、
前記第1スペーサの膜厚は、前記半導体チップの膜厚よりも大きい、半導体装置。 - 請求項1に記載の半導体装置において、
前記ヒートスラグは金属板からなる、半導体装置。 - 請求項1に記載の半導体装置において、
前記配線基板は、前記チップ搭載面にスペーサ搭載層を有し、前記第1スペーサは、前記スペーサ搭載層上に配置されている、半導体装置。 - 請求項7に記載の半導体装置において、
平面視において、前記スペーサ搭載層は第1スペーサの前記下面よりも広く、前記第1スペーサは接着剤を介して前記スペーサ搭載層に接着されている、半導体装置。 - 請求項7に記載の半導体装置において、
前記配線基板は、前記チップ搭載面から前記実装面に達するビア内配線を有し、前記スペーサ搭載層は、前記ビア内配線を介して前記外部電極端子に接続されている、半導体装置。 - 請求項1に記載の半導体装置において、さらに、
前記配線基板の前記チップ搭載面上であって、前記第1スペーサと異なる領域に配置され、前記ヒートスラグを支持する第2スペーサ、を有し、
前記第2スペーサの膜厚は、前記半導体チップの膜厚と前記第1スペーサの膜厚との和よりも大きい、半導体装置。 - チップ搭載面、前記チップ搭載面とは反対側の実装面、前記チップ搭載面上に形成された複数の第1電極パッドおよび複数の第2電極パッド、ならびに、前記実装面上に形成された複数の外部電極端子を有する配線基板と、
前記配線基板の前記チップ搭載面上に配置され、第1主面、前記第1主面とは反対側の第1裏面、および、前記第1主面上に形成された複数の第1ボンディングパッドを有する第1半導体チップと、
前記配線基板上の前記複数の第1電極パッドのそれぞれと前記第1半導体チップの前記第1ボンディングパッドのそれぞれを接続する複数の第1ワイヤと、
前記第1半導体チップの前記第1主面上に配置され、第1上面、および、前記第1上面とは反対側の第1下面を有する第1スペーサと、
前記第1スペーサの前記第1上面上に配置されたヒートスラグと、
前記配線基板の前記チップ搭載面上であって、前記第1半導体チップとは異なる領域に配置され、第2上面、および、前記第2上面と反対側の第2下面を有する第2スペーサと、
前記第2スペーサの前記第2上面上に配置され、第2主面、前記第2主面とは反対側の第2裏面、および、前記第2主面上に形成された複数の第2ボンディングパッドを有する第2半導体チップと、
前記配線基板上の前記複数の第2電極パッドのそれぞれと前記第2半導体チップの前記第2ボンディングパッドのそれぞれを接続する複数の第2ワイヤと、
前記配線基板の前記チップ搭載面、前記第1半導体チップ、前記第2半導体チップ、前記複数の第1ワイヤ、前記第2ワイヤ、前記第1スペーサ、前記第2スペーサ、および、前記ヒートスラグを覆う封止体と、
を有し、
前記ヒートスラグは、前記第2半導体チップの前記第2主面を覆い、
前記ヒートスラグと前記第2半導体チップの前記第2主面との間には前記封止体が介在する、半導体装置。 - 請求項11に記載の半導体装置において、
平面視において、前記ヒートスラグは、前記第1半導体チップの前記第1主面および前記第2半導体チップの前記第2主面を完全に覆っている、半導体装置。 - 請求項11に記載の半導体装置において、
平面視において、前記第1スペーサの前記第1上面は前記第1半導体チップの前記第1主面よりも小さく、前記第2スペーサの前記第2上面は前記第2半導体チップの前記第2主面よりも大きい、半導体装置。 - 請求項11に記載の半導体装置において、
前記第1半導体チップ、前記第2半導体チップ、前記第1スペーサおよび前記第2スペーサは、シリコンからなる、半導体装置。 - 請求項11に記載の半導体装置において、
前記ヒートスラグは金属板からなる、半導体装置。 - 請求項11に記載の半導体装置において、
前記第1半導体チップの膜厚と前記第1スペーサの膜厚との和は、前記第2半導体チップの膜厚と前記第2スペーサの膜厚との和よりも大きい、半導体装置。 - 請求項11に記載の半導体装置において、さらに、
前記第1半導体チップの前記第1主面と前記第1スペーサの前記第1下面との間に介在する第1接着剤と、
前記第1スペーサの前記第1上面と前記ヒートスラグとの間に介在する第2接着剤と、
を有し、前記第1接着剤はフィルム状接着剤であり、前記第2接着剤はペースト状接着剤である、半導体装置。 - 請求項11に記載の半導体装置において、さらに、
前記配線基板は、前記チップ搭載面に、複数の配線を有し、
前記第1半導体チップの前記第1主面と前記第2半導体チップの前記第2主面とは、一対の長辺と一対の短辺とを有する長方形であり、
前記第1半導体チップの一方の長辺と、前記第2半導体チップの一方の短辺とが互いに対向して配置されており、
前記一方の長辺に沿って配置された前記第1ボンディングパッドに電気的に接続された前記第1電極パッドと、前記一方の短辺に沿って配置された前記第2ボンディングパッドに電気的に接続された前記第2電極パッドとは、前記配線により電気的に接続されており、
前記配線は、前記一方の長辺および前記一方の短辺と直交する方向に延在する、半導体装置。 - 請求項11に記載の半導体装置において、
前記配線基板は、前記チップ搭載面にチップ搭載層およびスペーサ搭載層を有し、
前記第1半導体チップは前記チップ搭載層上に配置され、前記第2スペーサは前記スペーサ搭載層上に配置されている、半導体装置。 - 請求項19に記載の半導体装置において、
前記配線基板は、前記チップ搭載面から前記実装面に達する第1ビア内配線および第2ビア内配線を有し、
前記チップ搭載層は、前記第1ビア内配線を介して前記外部電極端子に接続され、
前記スペーサ搭載層は、前記第2ビア内配線を介して前記外部電極端子に接続されている、半導体装置。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001320014A (ja) * | 2000-05-11 | 2001-11-16 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2004241400A (ja) * | 2003-02-03 | 2004-08-26 | Denso Corp | 半導体装置 |
JP2005223008A (ja) * | 2004-02-03 | 2005-08-18 | Toshiba Corp | 半導体モジュール |
JP2007214602A (ja) * | 2007-05-28 | 2007-08-23 | Matsushita Electric Works Ltd | 半導体装置の製造方法 |
US20070205495A1 (en) * | 2004-08-02 | 2007-09-06 | Elstan Anthony Fernandez | Electronic Component With Stacked Semiconductor Chips And Heat Dissipating Means |
JP2014116382A (ja) * | 2012-12-07 | 2014-06-26 | J Devices:Kk | 半導体装置及びその製造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
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KR970005712B1 (ko) * | 1994-01-11 | 1997-04-19 | 삼성전자 주식회사 | 고 열방출용 반도체 패키지 |
TW411595B (en) * | 1999-03-20 | 2000-11-11 | Siliconware Precision Industries Co Ltd | Heat structure for semiconductor package device |
US6534859B1 (en) * | 2002-04-05 | 2003-03-18 | St. Assembly Test Services Ltd. | Semiconductor package having heat sink attached to pre-molded cavities and method for creating the package |
JP2012033559A (ja) | 2010-07-28 | 2012-02-16 | J Devices:Kk | 半導体装置 |
CN102569272B (zh) * | 2011-12-31 | 2014-06-25 | 天水华天科技股份有限公司 | 一种基板的多层隔片式ic芯片堆叠封装件及其生产方法 |
CN203134855U (zh) * | 2013-01-11 | 2013-08-14 | 华南师范大学 | 具有良好散热和高显色指数功率型led结构 |
-
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001320014A (ja) * | 2000-05-11 | 2001-11-16 | Seiko Epson Corp | 半導体装置及びその製造方法 |
JP2004241400A (ja) * | 2003-02-03 | 2004-08-26 | Denso Corp | 半導体装置 |
JP2005223008A (ja) * | 2004-02-03 | 2005-08-18 | Toshiba Corp | 半導体モジュール |
US20070205495A1 (en) * | 2004-08-02 | 2007-09-06 | Elstan Anthony Fernandez | Electronic Component With Stacked Semiconductor Chips And Heat Dissipating Means |
JP2007214602A (ja) * | 2007-05-28 | 2007-08-23 | Matsushita Electric Works Ltd | 半導体装置の製造方法 |
JP2014116382A (ja) * | 2012-12-07 | 2014-06-26 | J Devices:Kk | 半導体装置及びその製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2019165173A (ja) * | 2018-03-20 | 2019-09-26 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
WO2023026511A1 (ja) * | 2021-08-25 | 2023-03-02 | キオクシア株式会社 | 半導体装置及び電子機器 |
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