JP2016029711A - 半導体装置およびその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims description 70
- 238000004519 manufacturing process Methods 0.000 title claims description 12
- 150000004767 nitrides Chemical class 0.000 claims abstract description 96
- 230000001681 protective effect Effects 0.000 claims abstract description 78
- 239000002184 metal Substances 0.000 claims abstract description 37
- 229910052751 metal Inorganic materials 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000000463 material Substances 0.000 claims abstract description 20
- 239000010410 layer Substances 0.000 claims description 141
- 239000011229 interlayer Substances 0.000 claims description 47
- 238000000034 method Methods 0.000 claims description 16
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 14
- 238000000059 patterning Methods 0.000 claims description 8
- 229910052757 nitrogen Inorganic materials 0.000 claims description 7
- 238000007789 sealing Methods 0.000 claims description 6
- 230000035699 permeability Effects 0.000 claims description 4
- 239000012212 insulator Substances 0.000 abstract 7
- 230000001747 exhibiting effect Effects 0.000 abstract 2
- 230000002093 peripheral effect Effects 0.000 description 27
- 238000005530 etching Methods 0.000 description 10
- 238000000926 separation method Methods 0.000 description 8
- 238000004140 cleaning Methods 0.000 description 6
- 239000000047 product Substances 0.000 description 6
- 229910016570 AlCu Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000007795 chemical reaction product Substances 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 125000001495 ethyl group Chemical group [H]C([H])([H])C([H])([H])* 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
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- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
Description
本発明の第1実施形態について図面を参照しつつ説明する。半導体装置は、図1および図2に示されるように、素子部1、素子部1を取り囲む外周部2、外周部2を取り囲むシール部3を有しており、基板10の一面10a上に積層配線層20が配置された構成とされている。なお、図1は、図2中のI−I断面に相当しており、図2は、素子部1、外周部2、シール部3、後述するシール構造3a(シール層82)の配置関係を示す平面模式図である。
本発明の第2実施形態について説明する。本実施形態は、第1実施形態に対してシール構造3aの構成を変更したものであり、その他に関しては第1実施形態と同様であるため、ここでは説明を省略する。
本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。
3 シール部
3a シール構造
10 基板
10a 一面
20 積層配線層
31〜34 層間絶縁膜
41a〜43a 第1〜第3接続配線
41b〜43b 第1〜第3シール配線
51a〜53a 第1〜第3接続ビア
51b〜53b 第1〜第3シールビア
60 窒化膜
70 保護絶縁膜
82 シール層
Claims (11)
- 一面(10a)を有する基板(10)と、
前記基板の一面上に形成され、複数の層間絶縁膜(31〜34)と金属で構成された複数の配線層(41a、41b、51a、51b〜43a、43b、53a、53b)とが交互に積層された積層配線層(20)と、
前記積層配線層上に形成され、前記層間絶縁膜より水分の透過性が低い窒化膜(60)と、を備え、
前記基板の一面に対する法線方向から視たとき、半導体素子が形成される素子部(1)を取り囲むようにシール部(3)が配置され、前記シール部では、前記複数の配線層のうちの最も前記窒化膜側に位置する最上層配線層(43b)と接続されると共に金属で構成されたシール層(82)が配置され、前記複数の配線層と前記シール層とが接続されることによって前記素子部を取り囲むシール構造(3a)が構成されている半導体装置において、
前記積層配線層は、前記基板側と反対側の最上層が前記窒化膜より前記最上層配線層との密着性が高い材料で構成された最上層絶縁膜(34)とされ、
前記窒化膜上には、前記窒化膜より前記シール層との密着性が高い材料で構成された保護絶縁膜(70)が配置されており、
前記シール部では、前記保護絶縁膜、前記窒化膜、前記最上層絶縁膜に前記最上層配線層の一部を露出させるビアホール(70b、60b、34b)が形成され、前記シール層は前記ビアホールに埋め込まれていると共に、前記保護絶縁膜のうちの前記ビアホールの周囲に位置する部分上に渡って配置され、
前記シール構造の外側では、前記保護絶縁膜、前記窒化膜、前記最上層絶縁膜の一部が前記シール層および前記最上層配線層によって挟まれていることを特徴とする半導体装置。 - 前記最上層絶縁膜は、前記最上層配線層より前記窒化膜との密着性が高い材料で構成され、
前記保護絶縁膜は、前記シール層より前記窒化膜との密着性が高い材料で構成されていることを特徴とする請求項1に記載の半導体装置。 - 前記保護絶縁膜は、前記窒化膜より硬度が小さい材料にて構成されていることを特徴とする請求項1または2に記載の半導体装置。
- 前記保護絶縁膜は、前記窒化膜のうちの前記積層配線層側と反対側の部分を全て被覆していることを特徴とする請求項1ないし3のいずれか1つに記載の半導体装置。
- 前記保護絶縁膜は、窒素を含まない構成とされていることを特徴とする請求項1ないし4のいずれか1つに記載の半導体装置。
- 前記保護絶縁膜は、酸化膜であることを特徴とする請求項5に記載の半導体装置。
- 前記シール構造は、前記基板と絶縁されていることを特徴とする請求項1ないし6のいずれか1つに記載の半導体装置。
- 前記シール構造は、前記基板の一面に対する法線方向から視たとき、矩形枠状の角部が面取りされた形状とされていることを特徴とする請求項1ないし7のいずれか1つに記載の半導体装置。
- 前記基板は、支持基板(11)、絶縁膜(12)、半導体層(13)が順に積層されて構成されていることを特徴とする請求項1ないし8のいずれか1つに記載の半導体装置。
- 請求項1ないし9のいずれか1つに記載の半導体装置の製造方法において、
前記素子部および前記シール部を有するチップ領域を複数備えると共にそれぞれの前記チップ領域がスクライブ部(4)によって区画され、前記スクライブ部に沿って分割されることで前記基板を構成するウェハ(100)を用意する工程と、
前記ウェハの一面上に前記積層配線層を形成する工程と、
前記積層配線層上に前記窒化膜を形成する工程と、
前記窒化膜上に前記保護絶縁膜を形成する工程と、
前記シール部において、前記保護絶縁膜、前記窒化膜、前記最上層絶縁膜を貫通して前記最上層配線層の一部を露出させる前記ビアホールを形成する工程と、
前記ビアホールを埋め込みつつ、前記保護絶縁膜上に金属膜(80)を成膜する工程と、
前記金属膜をパターニングすることで前記シール層を形成することにより、前記複数の配線層と前記シール層とを有する前記シール構造を構成すると共に、前記シール構造の外側において、前記保護絶縁膜、前記窒化膜、前記最上層絶縁膜の一部が前記シール層および前記最上層配線層によって挟まれるようにするパターニング工程と、
前記ウェハをスクライブ部に沿ってチップ単位に分割する工程と、を行うことを特徴とする半導体装置の製造方法。 - 前記保護絶縁膜を形成する工程では、窒素を含まない前記保護絶縁膜を形成し、
前記保護絶縁膜を形成する工程および前記パターニング工程では、前記窒化膜のうちの前記積層配線層側と反対側の部分が全て前記保護絶縁膜にて被覆されるように、前記保護絶縁膜を形成すると共に、前記金属膜をドライエッチングすることを特徴とする請求項10に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2015127992A JP6406138B2 (ja) | 2014-07-18 | 2015-06-25 | 半導体装置およびその製造方法 |
US15/325,745 US9799612B2 (en) | 2014-07-18 | 2015-07-14 | Semiconductor device and manufacturing method of the same |
PCT/JP2015/003564 WO2016009645A1 (ja) | 2014-07-18 | 2015-07-14 | 半導体装置およびその製造方法 |
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JP2014147970 | 2014-07-18 | ||
JP2014147970 | 2014-07-18 | ||
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JP2008270232A (ja) * | 2005-07-08 | 2008-11-06 | Renesas Technology Corp | 半導体装置 |
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