JP2015537383A - 共用拡散標準セルの構造 - Google Patents
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- 238000009792 diffusion process Methods 0.000 title claims abstract description 84
- 239000004065 semiconductor Substances 0.000 claims abstract description 28
- 238000000034 method Methods 0.000 claims description 31
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 230000008878 coupling Effects 0.000 claims description 4
- 238000010168 coupling process Methods 0.000 claims description 4
- 238000005859 coupling reaction Methods 0.000 claims description 4
- 230000006870 function Effects 0.000 description 14
- 238000013461 design Methods 0.000 description 12
- 238000003860 storage Methods 0.000 description 11
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- 230000015654 memory Effects 0.000 description 8
- 238000004891 communication Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 6
- 230000008569 process Effects 0.000 description 4
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 238000006731 degradation reaction Methods 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 241001025261 Neoraja caerulea Species 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
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- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11803—Masterslice integrated circuits using field effect technology
- H01L27/11807—CMOS gate arrays
- H01L2027/11809—Microarchitecture
- H01L2027/11829—Isolation techniques
- H01L2027/11831—FET isolation
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Abstract
Description
[0025]1つの観点にしたがって、図3に示されたように、右端ダミーゲート318と左端ダミーゲート308の両方がタイオフされ得る。右端ダミーゲート318は、右端ゲートタイオフ316を介してタイオフされ得、ならびに左端ダミーゲート308は、左端ゲートタイオフ314を介してタイオフされ得る。2つのフィンガーセル構造において、電源はセルの両側にもたらされ得、その結果、両方のダミーゲートがタイオフされ得ることが留意されるべきである。図3のセル300のような2つのフィンガーセル構造は対称セルと称され得る。
Claims (20)
- セルにわたっておよび前記セルの外側にも延在するNタイプの拡散領域と、
前記セルにわたっておよび前記セルの外側にも延在するPタイプの拡散領域と、
半導体デバイスを生成するための、各拡散領域上方の少なくとも1つの導電ゲートと、
一対のダミーゲートと、各ダミーゲートは少なくとも一対のダミーデバイスを生成するために前記Nタイプの拡散領域と前記Pタイプの拡散領域上方に配置される、前記一対のダミーゲートは前記セルの反対側の端部に配置される、
および
前記少なくとも1つのダミーデバイスを無効にするための電源に前記ダミーデバイスのうちの少なくとも1つを結合するように構成された少なくとも1つの第1の導電線、
を備える半導体標準セル。 - 前記少なくとも1つの第1の導電線に結合された前記少なくとも1つのダミーデバイスは、前記セルの一端のみに配置される、請求項1に記載のセル。
- 前記少なくとも1つの第1の導電線に結合された前記少なくとも1つのダミーデバイスは、複数の導電線に結合された前記一対のダミーデバイスを備え、前記一対のダミーデバイスは、前記セルの反対側の端部に配置される、請求項1に記載のセル。
- 前記少なくとも1つの導電ゲートは、各拡散領域上方に複数の導電ゲートを備え、
および
前記セルは、前記複数の導電ゲートの間に配置された出力タブをさらに備える、請求項3に記載のセル。 - 各ダミーゲートは、一対のカットダミーゲートを備え、各カットダミーゲートは、前記Pタイプの拡散領域または前記Nタイプの拡散領域のいずれかと関連する、請求項1に記載のセル。
- 各カットダミーゲートは、PタイプのダミーデバイスまたはNタイプのダミーデバイスの一部を形成する、請求項5に記載のセル。
- グラウンドに前記ダミーデバイスのうちの少なくとも1つを結合するように構成された少なくとも1つの第2の導電線をさらに備え、前記少なくとも1つのダミーデバイスを無効にする、請求項1に記載のセル。
- セルにわたっておよび前記セルの外側にも延在するNタイプの拡散領域を製造することと、
前記セルにわたっておよび前記セルの外側にも延在するPタイプの拡散領域を製造することと、
半導体デバイスを生成するために、各拡散領域上方に少なくとも1つの導電ゲートを製造することと、
一対のダミーゲートを製造することと、各ダミーゲートは少なくとも一対のダミーデバイスを生成するために前記Nタイプの拡散領域と前記Pタイプの拡散領域上方に配置される、前記一対のダミーゲートは前記セルの反対側の端部に配置される、
および
前記少なくとも1つのダミーデバイスを無効にするための電源に前記ダミーデバイスのうちの少なくとも1つを結合するように構成された少なくとも1つの第1の導電線を製造すること、
を備える半導体セル製造方法。 - 前記少なくとも1つの第1の導電線を製造することは、前記少なくとも1つのダミーデバイスが前記セルの一端のみに配置されるように前記少なくとも1つの第1の導電線に前記少なくとも1つのダミーデバイスを結合することを備える、請求項8に記載の方法。
- 複数の導電線に前記一対のダミーデバイスを結合することをさらに備え、前記一対のダミーデバイスは、前記セルの反対側の端部に配置される、請求項8に記載の方法。
- 前記少なくとも1つの導電ゲートは、各拡散領域上方に複数の導電ゲートを備え、
および
前記方法は、前記複数の導電ゲートの間に配置された出力タブを製造することをさらに備える、請求項10に記載の方法。 - 一対のカットダミーゲートを製造するために前記ダミーゲートをカットすることをさらに備え、各カットダミーゲートは、前記Pタイプの拡散領域または前記Nタイプの拡散領域のいずれかと関連する、請求項8に記載の方法。
- 各カットダミーゲートは、PタイプのダミーデバイスまたはNタイプのダミーデバイスの一部を形成する、請求項12に記載の方法。
- 少なくとも1つの第2の導電線を製造することおよび前記少なくとも1つのダミーデバイスを無効にするために前記少なくとも1つの第2の導電線を介してグラウンドに前記ダミーデバイスの少なくとも1つを結合することをさらに備える、請求項8に記載の方法。
- セルにわたっておよび前記セルの外側にも延在するNタイプの拡散領域と、
前記セルにわたっておよび前記セルの外側にも延在するPタイプの拡散領域と、
半導体デバイスを生成するための、各拡散領域上方の少なくとも1つの導電ゲートと、
一対のダミーゲートと、各ダミーゲートは少なくとも一対のダミーデバイスを生成するために前記Nタイプの拡散領域と前記Pタイプの拡散領域上方に配置される、前記一対のダミーデバイスは前記セルの反対側の端部に配置される、
および
前記少なくとも1つのダミーデバイスを無効にするための電源に前記ダミーデバイスのうちの少なくとも1つを結合するための少なくとも1つの第1の導電手段、
を備える半導体標準セル。 - 前記少なくとも1つの第1の導電手段に結合された前記少なくとも1つのダミーデバイスは、前記セルの一端のみに配置される、請求項15に記載のセル。
- 前記少なくとも1つの第1の導電手段に結合された前記少なくとも1つのダミーデバイスは、複数の導電手段に結合された前記一対のダミーデバイスを備え、前記一対のダミーデバイスは、前記セルの反対側の端部に配置される、請求項15に記載のセル。
- 前記少なくとも1つの導電ゲートは、各拡散領域上方に複数の導電ゲートを備え、
および
前記セルは、信号を出力するための手段をさらに備え、前記出力手段は、前記複数の導電ゲートの間に配置される、請求項17に記載のセル。 - 各ダミーゲートは一対のカットダミーゲートを備え、各カットダミーゲートは、前記Nタイプの拡散または前記Pタイプの拡散領域のいずれかと関連する、請求項15に記載のセル。
- 各カットダミーゲートは、NタイプのダミーデバイスまたはPタイプのダミーデバイスの一部を形成する、請求項19に記載のセル。
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Application Number | Priority Date | Filing Date | Title |
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US13/671,114 US8836040B2 (en) | 2012-11-07 | 2012-11-07 | Shared-diffusion standard cell architecture |
US13/671,114 | 2012-11-07 | ||
PCT/US2013/068334 WO2014074459A1 (en) | 2012-11-07 | 2013-11-04 | Shared-diffusion standard cell architecture |
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JP2016172671A Division JP2017022395A (ja) | 2012-11-07 | 2016-09-05 | 共用拡散標準セルの構造 |
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JP2015540850A Withdrawn JP2015537383A (ja) | 2012-11-07 | 2013-11-04 | 共用拡散標準セルの構造 |
JP2016172671A Pending JP2017022395A (ja) | 2012-11-07 | 2016-09-05 | 共用拡散標準セルの構造 |
JP2018039659A Pending JP2018125542A (ja) | 2012-11-07 | 2018-03-06 | 共用拡散標準セルの構造 |
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JP2018039659A Pending JP2018125542A (ja) | 2012-11-07 | 2018-03-06 | 共用拡散標準セルの構造 |
Country Status (7)
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US (1) | US8836040B2 (ja) |
EP (1) | EP2917939B1 (ja) |
JP (3) | JP2015537383A (ja) |
KR (1) | KR101600960B1 (ja) |
CN (1) | CN104769718B (ja) |
TW (1) | TWI474469B (ja) |
WO (1) | WO2014074459A1 (ja) |
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JP2020145313A (ja) * | 2019-03-06 | 2020-09-10 | ユナイテッド・セミコンダクター・ジャパン株式会社 | 半導体装置及びその製造方法 |
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CN104769718A (zh) | 2015-07-08 |
US20140124868A1 (en) | 2014-05-08 |
EP2917939A1 (en) | 2015-09-16 |
WO2014074459A1 (en) | 2014-05-15 |
CN104769718B (zh) | 2019-08-09 |
EP2917939B1 (en) | 2021-06-23 |
TW201426974A (zh) | 2014-07-01 |
TWI474469B (zh) | 2015-02-21 |
KR20150066607A (ko) | 2015-06-16 |
JP2018125542A (ja) | 2018-08-09 |
US8836040B2 (en) | 2014-09-16 |
JP2017022395A (ja) | 2017-01-26 |
KR101600960B1 (ko) | 2016-03-08 |
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