JP2015525679A - Memsチップ及びその製造方法 - Google Patents
Memsチップ及びその製造方法 Download PDFInfo
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- JP2015525679A JP2015525679A JP2015518815A JP2015518815A JP2015525679A JP 2015525679 A JP2015525679 A JP 2015525679A JP 2015518815 A JP2015518815 A JP 2015518815A JP 2015518815 A JP2015518815 A JP 2015518815A JP 2015525679 A JP2015525679 A JP 2015525679A
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- oxide layer
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00777—Preserve existing structures from alteration, e.g. temporary protection during manufacturing
- B81C1/00825—Protect against mechanical threats, e.g. against shocks, or residues
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
- B81B7/00—Microstructural systems; Auxiliary parts of microstructural devices or systems
- B81B7/0009—Structural features, others than packages, for protecting a device against environmental influences
- B81B7/0029—Protection against environmental influences not provided for in groups B81B7/0012 - B81B7/0025
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00349—Creating layers of material on a substrate
- B81C1/0038—Processes for creating layers of materials not provided for in groups B81C1/00357 - B81C1/00373
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0161—Controlling physical properties of the material
- B81C2201/0163—Controlling internal stress of deposited layers
- B81C2201/0167—Controlling internal stress of deposited layers by adding further layers of materials having complementary strains, i.e. compressive or tensile strain
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/05—Temporary protection of devices or parts of the devices during manufacturing
- B81C2201/053—Depositing a protective layers
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Abstract
Description
110 シリコン基板層
112 シリコン基板層の前面
114 シリコン基板層の裏面
120 第1の酸化層
130 第1の薄膜層
140 第2の酸化層
150 第2の薄膜層
Claims (10)
- MEMSチップであって、
マイクロ電気機械プロセスのための前面と、前記前面の反対側に位置する裏面とを有し、前記前面及び前記裏面が両方とも研磨面であるシリコン基板層と、
前記シリコン基板層の裏面上に形成され、主としてSiO2から作られる第1の酸化層と、
前記第1の酸化層の表面上に形成され、主として窒化ケイ素から作られる第1の薄膜層と、
を備える、MEMSチップ。 - 前記シリコン基板層の前面上に形成された第2の酸化層を更に備える、請求項1に記載のMEMSチップ。
- 前記第1の薄膜層の厚さに対する前記第1の酸化層の厚さの比が3〜4の範囲にある、請求項2に記載のMEMSチップ。
- 前記第1の酸化層の厚さが400nmであり、前記第1の薄膜層の厚さが100nmであり、前記第2の酸化層の厚さが100nmである、請求項3に記載のMEMSチップ。
- 前記第2の酸化層の表面上に形成された第2の薄膜層を更に備え、前記第2の酸化層が前記第1の酸化層と同じ厚さを有し、前記第2の薄膜層が前記第1の薄膜層と同じ厚さを有する、請求項2に記載のMEMSチップ。
- MEMSチップを製造する方法であって、
マイクロ電気機械プロセスのための前面と、前記前面の反対側に位置する裏面とを有するシリコン基板層を設けるステップと、
熱酸化プロセスを実施することにより、前記シリコン基板層の裏面上に主としてSiO2から作られた第1の酸化層を成長させるステップと、
減圧化学蒸着プロセスを実施することによって前記第1の酸化層上に主として窒化ケイ素から作られた第1の薄膜層を堆積させるステップと、
を含む、方法。 - 熱酸化プロセスを実施することにより、前記シリコン基板層の前面上に主としてSiO2から作られた第2の酸化層を成長させるステップを更に含む、請求項6に記載の方法。
- 前記第1の薄膜層の厚さに対する前記第1の酸化層の厚さの比が3〜4の範囲にある、請求項7に記載の方法。
- 前記第1の酸化層の厚さが400nmであり、前記第1の薄膜層の厚さが100nmであり、前記第2の酸化層の厚さが100nmである、請求項8に記載の方法。
- 減圧化学蒸着プロセスを実施することによって前記第2の酸化層上に主として窒化ケイ素から作られた第2の薄膜層を堆積させるステップを更に含み、前記第2の酸化層が前記第1の酸化層と同じ厚さを有し、前記第2の薄膜層が前記第1の薄膜層と同じ厚さを有する、請求項7に記載の方法。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201210234964.3A CN103523738B (zh) | 2012-07-06 | 2012-07-06 | 微机电系统薄片及其制备方法 |
CN201210234964.3 | 2012-07-06 | ||
PCT/CN2013/078523 WO2014005496A1 (zh) | 2012-07-06 | 2013-06-29 | 一种mems薄片及其制造方法 |
Publications (2)
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JP2015525679A true JP2015525679A (ja) | 2015-09-07 |
JP6175134B2 JP6175134B2 (ja) | 2017-08-02 |
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JP2015518815A Active JP6175134B2 (ja) | 2012-07-06 | 2013-06-29 | Memsチップ及びその製造方法 |
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US (2) | US9580301B2 (ja) |
EP (1) | EP2857348B1 (ja) |
JP (1) | JP6175134B2 (ja) |
CN (1) | CN103523738B (ja) |
WO (1) | WO2014005496A1 (ja) |
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CN104555907B (zh) * | 2015-01-29 | 2017-01-04 | 苏州晶方半导体科技股份有限公司 | 键合方法以及键合结构 |
CN109003885A (zh) * | 2018-07-04 | 2018-12-14 | 上海晶盟硅材料有限公司 | 双面抛光外延片的制作方法、外延片及半导体器件 |
WO2020212835A1 (en) * | 2019-04-15 | 2020-10-22 | Lumus Ltd. | Method of fabricating a light-guide optical element |
CN113336182B (zh) * | 2021-05-19 | 2023-05-26 | 中山大学南昌研究院 | 一种微机电系统封装结构及其制备方法 |
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- 2013-06-29 EP EP13813814.4A patent/EP2857348B1/en active Active
- 2013-06-29 US US14/411,537 patent/US9580301B2/en active Active
- 2013-06-29 WO PCT/CN2013/078523 patent/WO2014005496A1/zh active Application Filing
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JPH0428887A (ja) * | 1990-05-24 | 1992-01-31 | Seiko Instr Inc | カンチレバーの製造方法 |
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US20170121175A1 (en) | 2017-05-04 |
US9580301B2 (en) | 2017-02-28 |
US10077188B2 (en) | 2018-09-18 |
JP6175134B2 (ja) | 2017-08-02 |
US20150151958A1 (en) | 2015-06-04 |
WO2014005496A1 (zh) | 2014-01-09 |
EP2857348A4 (en) | 2016-01-13 |
CN103523738B (zh) | 2016-07-06 |
EP2857348B1 (en) | 2019-06-19 |
EP2857348A1 (en) | 2015-04-08 |
CN103523738A (zh) | 2014-01-22 |
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