JP2015213194A - 少なくとも1つのチップとワイヤ要素をアセンブルする方法、変形する接続要素を有する電子チップ、複数のチップを製造する方法、及び、少なくとも1つのチップとワイヤ要素のアセンブリ - Google Patents
少なくとも1つのチップとワイヤ要素をアセンブルする方法、変形する接続要素を有する電子チップ、複数のチップを製造する方法、及び、少なくとも1つのチップとワイヤ要素のアセンブリ Download PDFInfo
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- JP2015213194A JP2015213194A JP2015146016A JP2015146016A JP2015213194A JP 2015213194 A JP2015213194 A JP 2015213194A JP 2015146016 A JP2015146016 A JP 2015146016A JP 2015146016 A JP2015146016 A JP 2015146016A JP 2015213194 A JP2015213194 A JP 2015213194A
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Abstract
【解決手段】電子チップとワイヤ要素とをアセンブルする方法の第1のステップは、ワイヤ要素5a、5bをチップの溝の中に配置することを備える。チップは第1の要素と第2の要素8´とで輪郭が形成されており、第1の要素と第2の要素とは接続要素6により接続され、接続要素は、塑性的に変形する材料を備える。第2のステップは、第1及び第2の要素をクランプし、ワイヤ要素が溝の中に固定されるまで接続要素を変形させることを備える。
【選択図】図8
Description
− チップの溝の中にワイヤ要素を配置するステップであって、チップは第1の要素と第2の要素とにより輪郭が形成され(delineate)、第1の要素と第2の要素とは接続要素により接続され、接続要素は塑性的に変形する(plastically deformable)材料を備えるような、配置ステップと、
− 第1の要素と第2の要素とをクランプするステップであって、ワイヤ要素の固定が溝の中に得られるまで接続要素(link element)を変形する、クランプステップ。
− 第1の要素及び第2の要素と、
− 第1の要素と第2の要素とを分離する接続要素と、
− 両端が開いており、第1の要素と第2の要素と接続要素とで輪郭が形成されている溝と、
− 溝に配置された電気接続パッドと。
− 変形する材料を介してアクティブプレートの上に配置された対向プレート(counterplate)により形成されたアセンブリを形成するステップであって、各アクティブ領域の平らな面において、アクティブ領域の端部の1つに沿って、空間(cavity)を形成する、形成ステップと、
− 複数のチップを形成するためにアクティブ領域の端部に沿ってアセンブリを切断する切断ステップであって、
切断の切断線は得られた空間を通過し、
切断後、複数のチップは、それぞれ、少なくとも、変形する材料により形成された接続要素により分離された第1の要素及び第2の要素と、チップの1つの表面の平らな面において、第1の要素と第2の要素と接続要素とにより輪郭が形成された溝とを備え、
電気接続パッドは溝の中に配置され、接続要素の変形する材料は、チップのクランプが行われている際、第1の要素と第2の要素とが接触する前にパッドまで押し出されることができる、
切断ステップと。
− 第1の要素と第2の要素とを備えるマイクロ電子チップと、
− 第1の要素と第2の要素との間に挟まれた電気伝導ワイヤ要素(electrically conductive wire)と、
− 第1の要素と第2の要素と接続要素とに接触する接続要素であって、ワイヤ要素を第1の要素と第2の要素とのうちの少なくとも1つに固定することに関わる(participate)接続要素と。
ワイヤ要素5aへパッド7aが入り込む深さは、好ましくはワイヤ要素5aの直径の20%を超えることがなく、これによって、アセンブリにストレスがかかった際、ワイヤ要素が十分な切断強度を維持することを可能にする。
ガイド手段19は、接続要素6の圧力を制限するストップを形成するために、さらに凸部10の高さI2よりも高い高さI10を有することができる。
− アクティブプレート13を調達するステップであって、アクティブプレートは複数のアクティブ領域を備え、各アクティブ領域は少なくとも1つの電子コンポーネントを備え、各アクティブ領域は、アクティブ領域の端部の1つの近傍に少なくとも1つの電気接続パッド7を備えることができ、言い換えると、アクティブ領域は、対応するアクティブ領域に電気的に接続した電気接続パッド7を有することができる、調達ステップと、
− 変形する材料を介してアクティブプレート13の上に配置された対向プレート11により構成されたアセンブリを形成するステップであって、各アクティブ領域の平らな面において、このアクティブ領域の端部の1つに沿って空間を形成し、パッド7を有する他の実施形態によれば、空間は、対応するパッドの端部に沿って形成されている、形成ステップと、
− 前記複数のチップを形成するためにアクティブ領域の端部に沿ってアセンブリを切断するステップであって、
切断の切断線は得られた空間を通過し、
切断後、複数のチップは、それぞれ、少なくとも、変形する材料により形成された接続要素6により分離された第1の要素8及び第2の要素8´と、このチップの1つの表面の平らな面にあって、第1の要素8と第2の要素8´と接続要素6とにより輪郭が形成された溝4a、4bとを備え、
この電気接続パッド7はこの溝4a、4bの中に配置され、接続要素6のこの変形する材料は、チップのクランプが行われている際、第1の要素8と第2の要素8´とが接触する前に押し出されることができる、
切断ステップと。
Claims (18)
- 電子チップとワイヤ要素をアセンブルする方法であって、以下のステップである、
− 前記チップの溝(4a、4b)の中に前記ワイヤ要素を配置するステップであって、前記チップは第1の要素(8)と第2の要素(8´)とにより輪郭が形成され、前記第1の要素と前記第2の要素とは接続要素(6)により接続され、前記接続要素は塑性的に変形する材料を備えるような、配置ステップと、
− 前記第1の要素(8)と前記第2の要素(8´)とをクランプするステップであって、前記ワイヤ要素の固定が前記溝の中に得られるまで前記接続要素(6)を変形する、クランプステップと、
を備える方法。 - 前記クランプステップ後に前記クランプを開放する開放ステップ備え、前記開放ステップ後に、前記接続要素(6)は変形した位置に維持される、ことを特徴とする請求項1に記載の方法。
- 前記溝の中の前記ワイヤ要素(5)の固定は、前記第1の要素(8)と前記第2の要素(8´)との間に前記ワイヤ要素(5)が機械的には挟まれることにより達成される、ことを特徴とする請求項1又は2に記載の方法。
- 前記溝(4a)の中の前記ワイヤ要素(5)の固定は、前記接続要素(6)が前記ワイヤ要素(5)と接触するまで変形する前記接続要素(6)により行われる、ことを特徴とする請求項1又は2に記載の方法。
- 前記接続要素(6)は熱可塑性又は熱硬化性材料から形成され、前記クランプは、80℃から260℃の間の温度において、5kg/cm2から30kg/cm2の間の圧力において行われる熱圧着であり、前記圧力は、前記アセンブリが凝固するような冷却期間の間も維持される、ことを特徴とする請求項1から4のいずれか1つに記載の方法。
- 電子チップであって、
− 第1の要素(8)及び第2の要素(8´)と、
− 前記第1の要素(8)と前記第2の要素(8´)とを分離する接続要素(6)と、 − 両端が開いており、前記第1の要素(8)と前記第2の要素(8´)と前記接続要素(6)とで輪郭が形成されている溝(4a、4b)と、
− 前記溝に配置された電気接続パッド(7)と
を備え、
前記接続要素(6)は材料を備え、前記材料は、前記第1の要素(8)と前記第2の要素(8´)との平らな面においてクランプすることにより塑性的に変形し、且つ、クランプが行われている際、前記第1の要素(8)と前記第2の要素(8´)とが接触する前に前記パッド(7)まで押し出されることができる、ことを特徴とするチップ。 - 前記チップはストップ(18)を備え、前記ストップは、クランプが行われている際、前記接続要素(6)の変形を制限する、ことを特徴とする請求項6に記載のチップ。
- 前記接続要素(6)の変形を制限する前記ストップは、前記第2の要素(8´)に向かい合う前記第1の要素(8)の表面の上に配置される、ことを特徴とする請求項7に記載のチップ。
- 前記第1の要素(8)は凸部(10)を備え、前記凸部は前記接続要素(6)とともに前記溝(4a)の前記底面(9c)を形成する、ことを特徴とする請求項6に記載のチップ。
- 前記第2の要素(8´)は前記凸部(10)のガイド手段(19)を備える、ことを特徴とする請求項9に記載のチップ。
- 前記ストップは前記凸部(10)と前記ガイド手段(19)とによって形成される、ことを特徴とする請求項10及び7に記載のチップ。
- 前記接続要素(6)は、熱可塑性高分子材料又は熱硬化性高分子材料又は可溶性材料から形成される、ことを特徴とする請求項6から11のいずれか1つに記載のチップ。
- 複数の電子チップを製造する方法であって、以下のステップである、
− アクティブプレート(13)を調達するステップであって、前記アクティブプレートは複数のアクティブ領域を備え、前記各アクティブ領域は少なくとも1つの電子コンポーネントと、対応する前記アクティブ領域に接続した電気接続パッド(7)とを有する、調達ステップと、
− 変形する材料を介して前記アクティブプレート(13)の上に配置された対向プレート(11)により形成されたアセンブリを形成するステップであって、前記各アクティブ領域の平らな面において、前記アクティブ領域の端部の1つに沿って、空間を形成する、形成ステップと、
− 前記複数のチップを形成するために前記アクティブ領域の端部に沿って前記アセンブリを切断する切断ステップであって、
前記切断の切断線は得られた前記空間を通過し、
前記切断後、前記複数のチップは、それぞれ、少なくとも、前記変形する材料により形成された接続要素(6)により分離された第1の要素(8)及び第2の要素(8´)と、前記チップの1つの表面の平らな面にあって、前記第1の要素(8)と前記第2の要素(8´)と前記接続要素(6)とにより輪郭が形成された溝(4a、4b)とを備え、
前記電気接続パッド(7)は前記溝(4a、4b)の中に配置され、前記接続要素(6)の前記変形する材料は、前記チップのクランプが行われている際、前記第1の要素(8)と前記第2の要素(8´)とが接触する前に前記パッド(7)まで押し出されることができる、
切断ステップと
を備えることを特徴とする製造方法。 - 前記対向プレートが前記アクティブプレートの上に移される前に、前記対向プレート(11)に実質的に平行なトレンチ(12)を形成するステップを備える、ことを特徴とする請求項13に記載の複数のチップを製造する方法。
- 前記トレンチ(12)が形成される前に、前記接続要素(6)を形成する前記材料は、前記対向プレート(11)の上に堆積される、ことを特徴とする請求項14に記載の方法。
- 前記トレンチ(12)を形成した後、前記対向プレート(11)は、液体状態の熱硬化性高分子又は熱可塑性高分子によって浸漬され、前記高分子は、前記対向プレート(11)が前記アクティブプレート(13)の上に移される前に、乾燥される、ことを特徴とする請求項14に記載の方法。
- 前記接続要素(6)を形成する前記材料は、前記トレンチを前記対向プレート(11)中に形成した後、前記対向プレート(11)と前記アクティブプレート(13)との間に配置された熱可塑性膜である、ことを特徴とする請求項14に記載の方法。
- − 第1の要素(8)と第2の要素(8´)とを備えるマイクロ電子チップと、
− 前記第1の要素(8)と前記第2の要素(8´)との間に挟まれた電気伝導ワイヤ要素(5)と、
− 前記第1の要素(8)と前記第2の要素(8´)と前記接続要素(5)とに接触する接続要素(6)であって、前記ワイヤ要素を前記第1の要素(8)と前記第2の要素(8´)とのうちの少なくとも1つに固定することに関わる接続要素と、
を備えるアセンブリ。
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FR3053157B1 (fr) | 2016-06-22 | 2018-10-12 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Boitier de dispositif microelectronique |
FR3062237B1 (fr) * | 2017-01-23 | 2020-05-01 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de realisation d’une puce a circuit integre et puce a circuit integre. |
FR3062515B1 (fr) * | 2017-01-30 | 2019-11-01 | Primo1D | Procede d'insertion d'un fil dans une rainure d'une puce de semi-conducteur, et equipement pour la mise en œuvre d’un tel procede. |
FR3065578B1 (fr) * | 2017-04-19 | 2019-05-03 | Primo1D | Procede d'assemblage d'une puce microelectronique sur un element filaire |
FR3076071B1 (fr) * | 2017-12-21 | 2019-11-15 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Procede de fabrication d’une puce a circuit integre et puce a circuit integre |
FR3083643B1 (fr) * | 2018-07-04 | 2023-01-13 | Commissariat Energie Atomique | Procede de realisation d'un dispositif electronique |
US20230223367A1 (en) * | 2022-01-12 | 2023-07-13 | Changxin Memory Technologies, Inc. | Semiconductor structure and method for manufacturing semiconductor structure |
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2009
- 2009-12-23 FR FR0906333A patent/FR2954588B1/fr not_active Expired - Fee Related
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2010
- 2010-12-21 EP EP10354095.1A patent/EP2339618B1/fr not_active Not-in-force
- 2010-12-22 JP JP2010285714A patent/JP5885921B2/ja not_active Expired - Fee Related
- 2010-12-23 CN CN201010603035.6A patent/CN102110677B/zh not_active Expired - Fee Related
- 2010-12-23 US US12/977,460 patent/US8654540B2/en not_active Expired - Fee Related
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- 2015-07-23 JP JP2015146016A patent/JP2015213194A/ja active Pending
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US20090200066A1 (en) * | 2006-08-29 | 2009-08-13 | Commissariat A L'energie Atomique | Bare microelectronic chip provided with a recess forming a housing for a wire element constituting a flexible mechanical support, fabrication process and microstructure |
JP2009200270A (ja) * | 2008-02-22 | 2009-09-03 | Panasonic Corp | 半導体装置および半導体装置の製造方法 |
WO2009112644A1 (fr) * | 2008-03-06 | 2009-09-17 | Commissariat A L'energie Atomique | Assemblage d'un élément filaire avec une puce microélectronique à rainure comportant au moins un plot de maintien de l'élément filaire |
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US8654540B2 (en) | 2014-02-18 |
JP5885921B2 (ja) | 2016-03-16 |
FR2954588B1 (fr) | 2014-07-25 |
US20110149540A1 (en) | 2011-06-23 |
EP2339618A2 (fr) | 2011-06-29 |
CN102110677A (zh) | 2011-06-29 |
EP2339618B1 (fr) | 2018-12-19 |
FR2954588A1 (fr) | 2011-06-24 |
CN102110677B (zh) | 2016-03-30 |
EP2339618A3 (fr) | 2012-10-17 |
JP2011135083A (ja) | 2011-07-07 |
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