JP2015213187A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2015213187A JP2015213187A JP2015132868A JP2015132868A JP2015213187A JP 2015213187 A JP2015213187 A JP 2015213187A JP 2015132868 A JP2015132868 A JP 2015132868A JP 2015132868 A JP2015132868 A JP 2015132868A JP 2015213187 A JP2015213187 A JP 2015213187A
- Authority
- JP
- Japan
- Prior art keywords
- gate
- insulating layer
- protrusion
- contact
- additional
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims description 25
- 238000011960 computer-aided design Methods 0.000 claims description 7
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract 3
- 238000012545 processing Methods 0.000 description 11
- 238000005516 engineering process Methods 0.000 description 7
- 238000013461 design Methods 0.000 description 6
- 238000001459 lithography Methods 0.000 description 4
- 238000011161 development Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 238000005452 bending Methods 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000013386 optimize process Methods 0.000 description 2
- 238000011165 process development Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 238000000342 Monte Carlo simulation Methods 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 230000001010 compromised effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005286 illumination Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823456—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
(a)接触部106Aとゲート102Aとの重なりの最小量(図3の矢印A);
(b)接触部106Aとゲート102Bとの間隔の最小量(図3の矢印B);
(c)接触部106AとM1構造104Aとの重なりの最小量(図3の矢印C);
(d)接触部106Aと追加M1構造110との間隔の最小量(図3の矢印D);
(e)接触部106Aと接触部112Bとの間隔の最小量(図3の矢印E);及び
(f)接触部106Aと活性領域114Bとの間隔の最小量(図3の矢印F)。
Claims (23)
- 半導体基板上のゲートであって、該ゲートの1つの側壁が少なくとも1つの突出部を有し、前記ゲートの反対側壁が少なくとも1つの凹部を有するゲートと、
前記ゲート上に実質的に配置された絶縁層と、
前記絶縁層を貫いて形成された接触部であって、前記ゲートの中の前記少なくとも1つの突出部に少なくとも部分的に重なった接触部と、
前記絶縁層上に配置された金属層であって、該金属層は前記ゲートの第1の側に移動した第1の構造を有し、前記接触部が前記絶縁層を通して該第1の構造を前記ゲートに電気的に連結するように、前記第1の構造は前記接触部に少なくとも部分的に重なっている金属層と、
を有する、半導体装置。 - 前記少なくとも1つの突出部と前記少なくとも1つの凹部とは、前記ゲートの長さの一部に沿って実質的に互いに対向している、請求項1に記載の装置。
- 前記突出部と前記凹部とは、前記ゲートの前記長さのすべてではなく一部に沿って実質的に互いに対向している、請求項2に記載の装置。
- 前記第1の構造は、前記ゲートの前記少なくとも1つの突出部に少なくとも部分的に重なっている、請求項1に記載の装置。
- 前記第1の構造は、前記ゲートに対向する該第1の構造の他の側の追加ゲートに重なっていない、請求項1に記載の装置。
- 前記ゲートの前記少なくとも突出部及び前記ゲートの前記少なくとも1つの凹部は、前記金属層の第2の構造が前記ゲートと少なくとも1つの追加ゲートの間に配置されることを可能にする、請求項1に記載の装置。
- 前記ゲートの前記第1の側とは反対側の該ゲートの第2の側に配置された前記金属層の第2の構造を更に有し、該第2の構造は前記第1の構造から電気的に絶縁されている、請求項1に記載の装置。
- 前記第2の構造は前記ゲートに重なっていない、請求項7に記載の装置。
- 前記第2の構造は、前記ゲートに対向する該第2の構造の前記側の追加ゲートに重なっていない、請求項7に記載の装置。
- 前記半導体基板上の追加ゲートを更に有し、該追加ゲートは、前記ゲートからは前記第2の構造の前記反対側に配置され、該第2の構造は前記ゲート又は前記追加ゲートに重なっていない、請求項7に記載の装置。
- 前記絶縁層に形成された少なくとも1つの追加接触部を更に有し、該追加接触部は、前記絶縁層を通して当該装置の活性領域を前記第2の構造に連結するように構成されている、請求項7に記載の装置。
- 前記ゲートの前記突出部と前記凹部は、CAD(コンピュータ支援設計)で設計されたパターンにより形成されている、請求項1に記載の装置。
- 半導体基板上にゲートを形成することであって、該ゲートの1つの側壁が少なくとも1つの突出部を有し、前記ゲートの反対側壁が少なくとも1つの凹部を有することと、
前記ゲート上に実質的に絶縁層を形成することと、
該絶縁層を通して接触部を形成することであって、該接触部は、前記ゲートの前記少なくとも1つの突出部に少なくとも部分的に重なることと、
前記絶縁層上に金属層を形成することであって、該金属層は前記ゲートの第1の側に移動した第1の構造を有し、前記接触部が前記絶縁層を通して該第1の構造を前記ゲートに電気的に連結するように、前記第1の構造は前記接触部に少なくとも部分的に重なることと、
を有する、半導体装置製造プロセス。 - 前記少なくとも1つの突出部と前記少なくとも1つの凹部とを前記ゲートの長さの一部に沿って実質的に互いに対向するように形成することを更に有する、請求項13に記載のプロセス。
- 前記突出部と前記凹部とは、前記ゲートの前記長さのすべてではなく一部に沿って実質的に互いに対向する、請求項14に記載のプロセス。
- 前記第1の構造が、前記ゲートに対向する該第1の構造の他の側の追加ゲートに重ならないように、前記第1の構造を配置することを更に有する、請求項13に記載のプロセス。
- 前記ゲートの前記第1の側とは反対側の該ゲートの第2の側に配置された前記金属層に第2の構造を形成することを更に有する、請求項13に記載のプロセス。
- 前記第2の構造が前記ゲートに重ならないように該第2の構造を配置することを更に有する、請求項17に記載のプロセス。
- 前記第2の構造が、前記ゲートに対向する該第2の構造の他の側の追加ゲートに重ならないように、前記第2の構造を配置することを更に有する、請求項17に記載のプロセス。
- 前記半導体基板上に追加ゲートを形成することを更に有し、該追加ゲートは、前記ゲートからは前記第2の構造の前記反対側に配置され、該第2の構造は前記ゲート又は前記追加ゲートに重ならない、請求項17に記載のプロセス。
- 前記絶縁層を通して当該装置の活性領域を前記第2の構造に連結するように、前記絶縁層に少なくとも1つの追加接触部を形成することを更に有する、請求項17に記載のプロセス。
- CAD(コンピュータ支援設計)で設計されたパターンに基づき前記ゲートの前記突出部と前記凹部を形成することを更に有する、請求項13に記載のプロセス。
- 1以上の半導体装置を有する集積回路であって、該半導体装置の少なくとも1つは、
半導体基板上のゲートであって、該ゲートの1つの側壁が少なくとも1つの突出部を有し、前記ゲートの反対側壁が少なくとも1つの凹部を有するゲートと、
該ゲート上に実質的に配置された絶縁層と、
該絶縁層を通して形成された接触部であって、前記ゲートの前記少なくとも1つの突出部に少なくとも部分的に重なった接触部と、
前記絶縁層上に配置された金属層であって、該金属層は前記ゲートの第1の側に移動した第1の構造を有し、前記接触部が前記絶縁層を通して該第1の構造を前記ゲートに電気的に連結するように、前記第1の構造は前記接触部に少なくとも部分的に重なっている金属層と、
を有する、集積回路。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/551,019 US8258578B2 (en) | 2009-08-31 | 2009-08-31 | Handshake structure for improving layout density |
US12/551,019 | 2009-08-31 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012527900A Division JP2013503499A (ja) | 2009-08-31 | 2010-08-21 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2015213187A true JP2015213187A (ja) | 2015-11-26 |
JP5957127B2 JP5957127B2 (ja) | 2016-07-27 |
Family
ID=43012627
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012527900A Pending JP2013503499A (ja) | 2009-08-31 | 2010-08-21 | 半導体装置 |
JP2015132868A Active JP5957127B2 (ja) | 2009-08-31 | 2015-07-01 | 半導体装置 |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2012527900A Pending JP2013503499A (ja) | 2009-08-31 | 2010-08-21 | 半導体装置 |
Country Status (7)
Country | Link |
---|---|
US (1) | US8258578B2 (ja) |
EP (1) | EP2474032A1 (ja) |
JP (2) | JP2013503499A (ja) |
KR (1) | KR101647082B1 (ja) |
CN (1) | CN102648521B (ja) |
IN (1) | IN2012DN02513A (ja) |
WO (1) | WO2011025718A1 (ja) |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101865840B1 (ko) * | 2011-08-10 | 2018-06-08 | 삼성전자주식회사 | 반도체 소자 |
US8741763B2 (en) * | 2012-05-07 | 2014-06-03 | Globalfoundries Inc. | Layout designs with via routing structures |
US8987128B2 (en) * | 2012-07-30 | 2015-03-24 | Globalfoundries Inc. | Cross-coupling based design using diffusion contact structures |
US8872241B1 (en) | 2013-05-20 | 2014-10-28 | International Business Machines Corporation | Multi-direction wiring for replacement gate lines |
US9397218B2 (en) * | 2014-01-09 | 2016-07-19 | Marvell World Trade Ltd. | Method and apparatus for mitigating effects of parasitic capacitance in semiconductor devices |
US9704862B2 (en) | 2014-09-18 | 2017-07-11 | Samsung Electronics Co., Ltd. | Semiconductor devices and methods for manufacturing the same |
US10095825B2 (en) | 2014-09-18 | 2018-10-09 | Samsung Electronics Co., Ltd. | Computer based system for verifying layout of semiconductor device and layout verify method thereof |
US9767248B2 (en) | 2014-09-18 | 2017-09-19 | Samsung Electronics, Co., Ltd. | Semiconductor having cross coupled structure and layout verification method thereof |
US9811626B2 (en) | 2014-09-18 | 2017-11-07 | Samsung Electronics Co., Ltd. | Method of designing layout of semiconductor device |
US10026661B2 (en) | 2014-09-18 | 2018-07-17 | Samsung Electronics Co., Ltd. | Semiconductor device for testing large number of devices and composing method and test method thereof |
KR102288869B1 (ko) * | 2014-10-01 | 2021-08-10 | 삼성전자주식회사 | 시스템 온 칩 |
US9589955B2 (en) | 2014-10-01 | 2017-03-07 | Samsung Electronics Co., Ltd. | System on chip |
KR102254031B1 (ko) | 2014-10-10 | 2021-05-20 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
KR102307207B1 (ko) * | 2015-03-25 | 2021-10-05 | 삼성전자주식회사 | 전계 효과 트랜지스터를 포함하는 반도체 소자 |
KR102318410B1 (ko) * | 2015-04-01 | 2021-10-28 | 삼성전자주식회사 | 반도체 소자 및 이의 제조 방법 |
KR102633138B1 (ko) | 2016-10-17 | 2024-02-02 | 삼성전자주식회사 | 집적 회로 및 반도체 장치 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11233628A (ja) * | 1998-02-16 | 1999-08-27 | Mitsubishi Electric Corp | コンタクト構造の製造方法 |
JP2000124332A (ja) * | 1998-10-15 | 2000-04-28 | Toshiba Corp | 半導体装置の製造方法及び半導体装置 |
JP2005327898A (ja) * | 2004-05-14 | 2005-11-24 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US20060138561A1 (en) * | 2004-12-27 | 2006-06-29 | Jung-Woo Seo | Semiconductor device having raised cell landing pad and method of fabricating the same |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3795634B2 (ja) * | 1996-06-19 | 2006-07-12 | 株式会社東芝 | 半導体装置の製造方法 |
JPH1065027A (ja) | 1996-08-21 | 1998-03-06 | Ricoh Co Ltd | 半導体不揮発性記憶装置 |
JP2006253461A (ja) | 2005-03-11 | 2006-09-21 | Toshiba Corp | 半導体集積回路装置およびその製造方法 |
US7312490B2 (en) * | 2005-03-31 | 2007-12-25 | Intel Corporation | Vertical memory device and method |
TWI305675B (en) * | 2006-04-03 | 2009-01-21 | Nanya Technology Corp | Semiconductor device and fabrication thereof |
TW201007885A (en) * | 2008-07-18 | 2010-02-16 | Nec Electronics Corp | Manufacturing method of semiconductor device, and semiconductor device |
-
2009
- 2009-08-31 US US12/551,019 patent/US8258578B2/en active Active
-
2010
- 2010-08-21 JP JP2012527900A patent/JP2013503499A/ja active Pending
- 2010-08-21 CN CN201080046074.9A patent/CN102648521B/zh active Active
- 2010-08-21 KR KR1020127008416A patent/KR101647082B1/ko active IP Right Grant
- 2010-08-21 EP EP10748185A patent/EP2474032A1/en not_active Withdrawn
- 2010-08-21 WO PCT/US2010/046254 patent/WO2011025718A1/en active Application Filing
-
2012
- 2012-03-22 IN IN2513DEN2012 patent/IN2012DN02513A/en unknown
-
2015
- 2015-07-01 JP JP2015132868A patent/JP5957127B2/ja active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH11233628A (ja) * | 1998-02-16 | 1999-08-27 | Mitsubishi Electric Corp | コンタクト構造の製造方法 |
JP2000124332A (ja) * | 1998-10-15 | 2000-04-28 | Toshiba Corp | 半導体装置の製造方法及び半導体装置 |
JP2005327898A (ja) * | 2004-05-14 | 2005-11-24 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US20060138561A1 (en) * | 2004-12-27 | 2006-06-29 | Jung-Woo Seo | Semiconductor device having raised cell landing pad and method of fabricating the same |
Also Published As
Publication number | Publication date |
---|---|
CN102648521A (zh) | 2012-08-22 |
IN2012DN02513A (ja) | 2015-08-28 |
JP5957127B2 (ja) | 2016-07-27 |
KR20120068895A (ko) | 2012-06-27 |
WO2011025718A1 (en) | 2011-03-03 |
US8258578B2 (en) | 2012-09-04 |
EP2474032A1 (en) | 2012-07-11 |
CN102648521B (zh) | 2015-12-09 |
US20110049635A1 (en) | 2011-03-03 |
JP2013503499A (ja) | 2013-01-31 |
KR101647082B1 (ko) | 2016-08-09 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5957127B2 (ja) | 半導体装置 | |
TWI619204B (zh) | 積體電路中採用之自對準局部互連線用之方法、結構與設計 | |
US9292647B2 (en) | Method and apparatus for modified cell architecture and the resulting device | |
JP2011238746A (ja) | 半導体装置及びそのレイアウト作成方法 | |
US10147684B1 (en) | Integrated circuit devices | |
KR100824200B1 (ko) | 반도체 소자의 금속배선 | |
US8841774B2 (en) | Semiconductor device including a first wiring having a bending portion a via | |
JP4575274B2 (ja) | パターンレイアウト、レイアウトデータの生成方法及び半導体装置 | |
US9530731B2 (en) | Method of optical proximity correction for modifying line patterns and integrated circuits with line patterns modified by the same | |
JP2015198135A (ja) | 半導体装置の製造方法 | |
JP2007311501A (ja) | 半導体装置及びその設計方法 | |
TWI671882B (zh) | 半導體晶片及積體電路製造方法 | |
US9171898B2 (en) | Method for manufacturing semiconductor layout pattern, method for manufacturing semiconductor device, and semiconductor device | |
US20140337809A1 (en) | Method for forming semiconductor layout patterns, semiconductor layout patterns, and semiconductor structure | |
US20040188849A1 (en) | Semiconductor device and pattern generating method | |
JP2013115333A (ja) | 半導体装置およびその製造方法 | |
JP2015198136A (ja) | 半導体記憶装置及びその製造方法 | |
KR20090077195A (ko) | 반도체 소자 및 그 제조방법 | |
TW201439803A (zh) | 光學鄰近修正方法暨其所形成的積體電路佈局圖形 | |
JP2007129094A (ja) | 半導体装置 | |
JP2013239063A (ja) | ダミーパターンの設計方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20151102 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20160209 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20160502 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20160524 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20160617 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5957127 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |