JP2015177008A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2015177008A JP2015177008A JP2014052126A JP2014052126A JP2015177008A JP 2015177008 A JP2015177008 A JP 2015177008A JP 2014052126 A JP2014052126 A JP 2014052126A JP 2014052126 A JP2014052126 A JP 2014052126A JP 2015177008 A JP2015177008 A JP 2015177008A
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- electrode
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- hole
- conductive layer
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Abstract
【解決手段】実施形態によれば、第1面に半導体素子3が形成され貫通孔2cを有する半導体基板2と、前記半導体基板2の前記貫通孔2c内に形成される貫通電極11とを備え、前記貫通電極11は、前記貫通孔2cの側壁面に形成された絶縁膜10を介して、前記貫通孔2cの側壁面に形成された導電層11aと、前記貫通孔2cの前記導電層11aを介した内部に充填された電極層11bとからなり、前記導電層11aは、前記電極層11bの材料よりも柔らかい材料で形成され、前記電極層11bは、前記導電層11aの材料よりも高融点を有する材料で形成され、内部に前記半導体基板2の第2面の近傍で閉塞された空隙部11cを有する。
【選択図】図1
Description
以下、第1実施形態について図1から図4を参照して説明する。
図1は貫通電極を有する半導体装置1の縦断側面を模式的に示している。半導体基板であるシリコン基板2は、第1面である図中下面側に半導体素子3が形成されている。シリコン基板2は、半導体素子3を形成した後に厚さが例えば20〜40μm程度となるように研削されている。
図5は、第2実施形態を示すもので、第1実施形態と異なるところは、貫通電極11に代えて、半導体装置16に貫通電極17を設ける構成としたところである。第1実施形態では、応力緩和およびマイグレーションの課題を解決する構成として空隙部11cを有するニッケル層11bを採用している。この場合、ニッケル層11bのニッケル(Ni)は、磁性材料であるから、半導体装置1が高周波で動作させるものである場合には、貫通電極11の内部に電流が流れにくくなる表皮効果が起こり、貫通電極11の中心部での電流が低下して表層部分だけに流れるため、全体として抵抗が上昇することになる。
図6は、第3実施形態を示すもので、第2実施形態と異なるところは、貫通電極17に代えて、半導体装置18に貫通電極19を設ける構成としたところである。この実施形態では、半導体装置18を高周波で使用するものである場合に、貫通電極19として非磁性化したニッケル層19bを用いることで表皮効果による抵抗上昇の影響を抑制する構成としている。
図7は、第4実施形態を示すもので、第2実施形態と異なるところは、貫通電極17に代えて、半導体装置20に貫通電極21を設ける構成としたところである。この実施形態では、半導体装置20を高周波で使用するものである場合に、貫通電極21としてニッケル層21bの表層部分に非磁性化した微粒子層21baを形成し、その内側にニッケル層21bbを設ける構成としたところである。これにより、ニッケル層21bにおける表皮効果による抵抗上昇の影響を抑制する構成としている。
上記実施形態で説明したもの以外に次のような変形形態に適用することができる。
貫通電極11、17、19、21の形成は、ウエハ工程の終盤で行う所謂ビアラストの場合の半導体装置1、16、18、20の例で説明したが、他の製造工程を採用する所謂ビアファーストあるいはビアミドルの半導体装置に設ける貫通電極の場合にも適用することができる。
本発明のいくつかの実施形態を説明したが、これらの実施形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
Claims (5)
- 第1面に半導体素子が形成され貫通孔を有する半導体基板と、
前記半導体基板の前記貫通孔内に形成される貫通電極とを備え、
前記貫通電極は、前記貫通孔の側壁面に形成された絶縁膜を介して、前記貫通孔の側壁面に形成された導電層と、前記貫通孔の前記導電層を介した内部に充填された電極層とからなり、
前記導電層は、前記電極層の材料よりも柔らかい材料で形成され、
前記電極層は、前記導電層の材料よりも高融点を有する材料で形成され、内部に前記半導体基板の第2面の近傍で閉塞された空隙部を有することを特徴とする半導体装置。 - 請求項1に記載の半導体装置において、
前記導電層は、銅(Cu)で形成され、
前記電極層は、ニッケル(Ni)で形成されることを特徴とする半導体装置。 - 請求項1または2に記載の半導体装置において、
前記電極層は、少なくとも前記導電層側の面が非磁性化層で形成されていることを特徴とする半導体装置。 - 請求項3に記載の半導体装置において、
前記電極層の非磁性化層は、非磁性材料を含有することを特徴とする半導体装置。 - 請求項3に記載の半導体装置において、
前記電極層の非磁性化層は、微結晶化されることで非磁性化されていることを特徴とする半導体装置。
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