JP2015170669A - 配線基板、及び、配線基板の製造方法 - Google Patents
配線基板、及び、配線基板の製造方法 Download PDFInfo
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- JP2015170669A JP2015170669A JP2014043317A JP2014043317A JP2015170669A JP 2015170669 A JP2015170669 A JP 2015170669A JP 2014043317 A JP2014043317 A JP 2014043317A JP 2014043317 A JP2014043317 A JP 2014043317A JP 2015170669 A JP2015170669 A JP 2015170669A
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4697—Manufacturing multilayer circuits having cavities, e.g. for mounting components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09972—Partitioned, e.g. portions of a PCB dedicated to different functions; Boundary lines therefore; Portions of a PCB being processed separately or differently
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Structure Of Printed Boards (AREA)
Abstract
複数の電子部品を1つの貫通孔の内部に配設する際の電気的信頼性を向上させた配線基板、及び、配線基板の製造方法を提供することを課題とする。
【解決手段】
配線基板は、貫通孔が形成され、前記貫通孔の内部に並べて設けられる複数の単位配置領域の境界部において、前記貫通孔の内壁から平面視で前記貫通孔の内側に突出する突出部を有するコア層と、前記貫通孔の内部で、前記突出部によって互いに離間された状態で、前記複数の単位配置領域にそれぞれ収容される複数の電子部品と、前記貫通孔の内部に充填され、前記電子部品の少なくとも側面を保持する樹脂層とを含む。
【選択図】図1
Description
図1は、実施の形態の配線基板100を示す断面図である。以下では、直交座標系の一例として、配線基板100の表面及び裏面と平行なXY平面を含むXYZ座標系を用いて説明を行う。図1は、配線基板100のY軸方向の中央を通るXZ平面に平行な断面を示す。
110、110X コア
110A、110AX 突出部
110BX 内壁
110H、110HX 貫通孔
111A 配線層
120A、120B 貫通電極
130A、130B 絶縁層
140A1、140A2、140A3、140A4、140A5、140A6、140B1、140B2、140B3、140B4、140B5、140B6 ビア
150A1、150A2、150A3、150A4、150A5、150A6、150B1、150B2、150B3、150B4、150B5、150B6 配線層
160A、160B ソルダーレジスト層
200 キャパシタチップ
Claims (10)
- 貫通孔が形成され、前記貫通孔の内部に並べて設けられる複数の単位配置領域の境界部において、前記貫通孔の内壁から平面視で前記貫通孔の内側に突出する突出部を有するコア層と、
前記貫通孔の内部で、前記突出部によって互いに離間された状態で、前記複数の単位配置領域にそれぞれ収容される複数の電子部品と、
前記貫通孔の内部に充填され、前記電子部品の少なくとも側面を保持する樹脂層と
を含む、配線基板。 - 前記貫通孔は平面視で矩形状であり、前記突出部は、前記境界部において前記複数の単位配置領域が並べられる方向に対する側方に位置する一対の前記内壁から突出している、請求項1記載の配線基板。
- 前記一対の内壁から突出する一対の突出部同士の間隔は、前記複数の単位配置領域が並べられる方向における前記電子部品の幅より狭い、請求項2記載の配線基板。
- 前記突出部の突出方向と前記コア層の厚さ方向とで規定される前記突出部の断面の形状は、前記コア層の両方の面からテーパ状に形成される形状である、請求項1乃至3のいずれか一項記載の配線基板。
- 前記コア層の平面に平行な前記突出部の断面の形状は、当該突出部の両側に位置する一対の前記単位配置領域の内壁面からテーパ状に突出する形状である、請求項1乃至4のいずれか一項記載の配線基板。
- 前記電子部品は直方体状であり、長手方向の両端に電極が形成される、請求項1乃至5のいずれか一項記載の配線基板。
- 前記電子部品は直方体状であり、前記電子部品の長手方向に前記複数の電子部品が配列される、請求項1乃至6のいずれか一項記載の配線基板。
- 前記電子部品は直方体状であり、前記電子部品の短手方向に前記複数の電子部品が配列される、請求項1乃至6のいずれか一項記載の配線基板。
- 前記電子部品はキャパシタチップである、請求項1乃至8のいずれか一項記載の配線基板。
- 貫通孔の内部に並べて設けられる複数の単位配置領域の境界部において内壁から平面視で内側に突出する突出部を有する前記貫通孔をコア層に形成する工程と、
前記貫通孔の内部の前記複数の単位配置領域に、前記突出部によって互いに離間された状態で、複数の電子部品をそれぞれ配置する工程と、
前記貫通孔の内部に樹脂材料を充填することにより、前記電子部品の少なくとも側面を保持する樹脂層を形成する工程と
を含む、配線基板の製造方法。
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JP2014043317A JP6373605B2 (ja) | 2014-03-05 | 2014-03-05 | 配線基板、及び、配線基板の製造方法 |
US14/634,972 US9560768B2 (en) | 2014-03-05 | 2015-03-02 | Wiring substrate and method of making wiring substrate |
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JP2014043317A JP6373605B2 (ja) | 2014-03-05 | 2014-03-05 | 配線基板、及び、配線基板の製造方法 |
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JP2015170669A true JP2015170669A (ja) | 2015-09-28 |
JP2015170669A5 JP2015170669A5 (ja) | 2017-02-09 |
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JP2019192730A (ja) * | 2018-04-23 | 2019-10-31 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
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JP6639934B2 (ja) * | 2016-02-08 | 2020-02-05 | 新光電気工業株式会社 | 配線基板、半導体装置及び配線基板の製造方法 |
JP2017175000A (ja) * | 2016-03-24 | 2017-09-28 | ローム株式会社 | 電子部品およびその製造方法、ならびに、インターポーザ |
JP6748501B2 (ja) * | 2016-07-14 | 2020-09-02 | ローム株式会社 | 電子部品およびその製造方法 |
CN112201652A (zh) * | 2019-07-07 | 2021-01-08 | 深南电路股份有限公司 | 线路板及其制作方法 |
KR20210076584A (ko) * | 2019-12-16 | 2021-06-24 | 삼성전기주식회사 | 전자부품 내장기판 |
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JP2012164952A (ja) * | 2011-01-20 | 2012-08-30 | Ibiden Co Ltd | 電子部品内蔵配線板及びその製造方法 |
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JP2012079994A (ja) * | 2010-10-05 | 2012-04-19 | Yamaichi Electronics Co Ltd | 部品内蔵プリント配線板およびその製造方法 |
US8957320B2 (en) * | 2011-10-11 | 2015-02-17 | Ibiden Co., Ltd. | Printed wiring board |
US9439289B2 (en) * | 2012-01-12 | 2016-09-06 | Ibiden Co., Ltd. | Wiring board and method for manufacturing the same |
KR102080663B1 (ko) * | 2013-07-15 | 2020-02-24 | 삼성전기주식회사 | 전자소자 내장형 인쇄회로기판 및 그 제조방법 |
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JP6334962B2 (ja) * | 2014-03-05 | 2018-05-30 | 新光電気工業株式会社 | 配線基板、及び、配線基板の製造方法 |
JP2015185828A (ja) * | 2014-03-26 | 2015-10-22 | イビデン株式会社 | 電子部品内蔵多層配線板およびその製造方法 |
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Patent Citations (3)
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JP2012164952A (ja) * | 2011-01-20 | 2012-08-30 | Ibiden Co Ltd | 電子部品内蔵配線板及びその製造方法 |
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JP2014003087A (ja) * | 2012-06-15 | 2014-01-09 | Shinko Electric Ind Co Ltd | 配線基板及びその製造方法 |
Cited By (2)
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JP6997670B2 (ja) | 2018-04-23 | 2022-01-17 | 新光電気工業株式会社 | 配線基板及びその製造方法 |
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US9560768B2 (en) | 2017-01-31 |
US20150257275A1 (en) | 2015-09-10 |
JP6373605B2 (ja) | 2018-08-15 |
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