JP2015103611A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2015103611A JP2015103611A JP2013241987A JP2013241987A JP2015103611A JP 2015103611 A JP2015103611 A JP 2015103611A JP 2013241987 A JP2013241987 A JP 2013241987A JP 2013241987 A JP2013241987 A JP 2013241987A JP 2015103611 A JP2015103611 A JP 2015103611A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 711
- 239000000758 substrate Substances 0.000 claims abstract description 296
- 230000015572 biosynthetic process Effects 0.000 claims description 268
- 229910052751 metal Inorganic materials 0.000 claims description 78
- 239000002184 metal Substances 0.000 claims description 78
- 239000010410 layer Substances 0.000 description 213
- 239000013256 coordination polymer Substances 0.000 description 78
- 239000004020 conductor Substances 0.000 description 40
- 239000012535 impurity Substances 0.000 description 39
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 37
- 238000000034 method Methods 0.000 description 35
- 229910052782 aluminium Inorganic materials 0.000 description 27
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 27
- 238000002955 isolation Methods 0.000 description 25
- 238000007789 sealing Methods 0.000 description 25
- 238000004519 manufacturing process Methods 0.000 description 24
- 229910052721 tungsten Inorganic materials 0.000 description 23
- 239000010937 tungsten Substances 0.000 description 23
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 22
- 229910021332 silicide Inorganic materials 0.000 description 21
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 21
- 101001046426 Homo sapiens cGMP-dependent protein kinase 1 Proteins 0.000 description 20
- 102100022422 cGMP-dependent protein kinase 1 Human genes 0.000 description 20
- 239000000463 material Substances 0.000 description 15
- SGUKUZOVHSFKPH-UHFFFAOYSA-N PGG2 Natural products C1C2OOC1C(C=CC(OO)CCCCC)C2CC=CCCCC(O)=O SGUKUZOVHSFKPH-UHFFFAOYSA-N 0.000 description 14
- 239000012790 adhesive layer Substances 0.000 description 14
- 230000004888 barrier function Effects 0.000 description 14
- 238000005530 etching Methods 0.000 description 14
- SGUKUZOVHSFKPH-YNNPMVKQSA-N prostaglandin G2 Chemical compound C1[C@@H]2OO[C@H]1[C@H](/C=C/[C@@H](OO)CCCCC)[C@H]2C\C=C/CCCC(O)=O SGUKUZOVHSFKPH-YNNPMVKQSA-N 0.000 description 14
- 238000000206 photolithography Methods 0.000 description 13
- 125000006850 spacer group Chemical group 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 239000010949 copper Substances 0.000 description 12
- 230000009467 reduction Effects 0.000 description 12
- 229910052814 silicon oxide Inorganic materials 0.000 description 12
- 239000011229 interlayer Substances 0.000 description 11
- 230000001681 protective effect Effects 0.000 description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 10
- 230000004048 modification Effects 0.000 description 9
- 238000012986 modification Methods 0.000 description 9
- 239000002344 surface layer Substances 0.000 description 9
- 229910000838 Al alloy Inorganic materials 0.000 description 8
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 8
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- 229910052802 copper Inorganic materials 0.000 description 8
- 101100395484 Arabidopsis thaliana HPD gene Proteins 0.000 description 7
- 101100463166 Oryza sativa subsp. japonica PDS gene Proteins 0.000 description 7
- 101150061817 PDS1 gene Proteins 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 238000005468 ion implantation Methods 0.000 description 7
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 7
- 229920005591 polysilicon Polymers 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 230000007423 decrease Effects 0.000 description 5
- 239000007769 metal material Substances 0.000 description 5
- 238000004806 packaging method and process Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229910045601 alloy Inorganic materials 0.000 description 4
- 239000000956 alloy Substances 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 230000012447 hatching Effects 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 230000003252 repetitive effect Effects 0.000 description 4
- 229920005989 resin Polymers 0.000 description 4
- 239000011347 resin Substances 0.000 description 4
- 238000009751 slip forming Methods 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000003321 amplification Effects 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000001747 exhibiting effect Effects 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000003199 nucleic acid amplification method Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 229910021364 Al-Si alloy Inorganic materials 0.000 description 1
- 229910018182 Al—Cu Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 150000002736 metal compounds Chemical class 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- -1 tungsten nitride Chemical class 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/4824—Pads with extended contours, e.g. grid structure, branch structure, finger structure
-
- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49548—Cross section geometry
- H01L23/49551—Cross section geometry characterised by bent parts
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
- H01L23/49562—Geometry of the lead-frame for devices being provided for in H01L29/00
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- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
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- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
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- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
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- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
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- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
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- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
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- H01L29/41725—Source or drain electrodes for field effect devices
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- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/4175—Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/66689—Lateral DMOS transistors, i.e. LDMOS transistors with a step of forming an insulating sidewall spacer
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- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7809—Vertical DMOS transistors, i.e. VDMOS transistors having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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Abstract
【解決手段】半導体基板SUBに複数の単位LDMOSFET10aが形成され、複数の単位LDMOSFET10aのそれぞれのソース領域は、ソース配線M1Sおよびソース配線M2Sを介して互いに電気的に接続されている。複数の単位LDMOSFET10aのそれぞれのゲート電極GEは、ゲート配線M1Gを介して互いに電気的に接続され、かつ、ゲート配線M1Gを介してソース配線M2Sと同層のゲート配線に電気的に接続されている。複数の単位LDMOSFET10aのそれぞれのドレイン領域は、半導体基板SUBの溝TRに埋め込まれた導電性のプラグTLを介して裏面電極BEと電気的に接続されることにより、互いに電気的に接続されている。ソース配線M1Sおよびゲート配線M1Gの各厚みは、ソース配線M2Sの厚みよりも小さく、プラグTLの上方にゲート配線M1Gが延在している。
【選択図】図8
Description
<半導体装置の構造について>
本実施の形態の半導体装置を、図面を参照して説明する。図1は、本実施の形態の半導体装置(半導体チップ)CPの全体平面図であり、半導体装置CPの上面側の全体平面図が示されている。また、図2〜図4も、本実施の形態1の半導体装置CPの全体平面図であるが、図1とは異なる層が示されている。図5〜図7は、本実施の形態の半導体装置CPの要部平面図である。図1に示される二点鎖線で囲まれた領域RG1を拡大したものが、図5〜図7に対応しているが、図5〜図7は、互いに異なる層が示されている。図8〜図11は、本実施の形態の半導体装置CPの要部断面図である。
次に、半導体基板SUBに形成されたLDMOSFETと半導体基板SUB上に形成された配線M1,M2の平面レイアウトについて説明する。
次に、本実施の形態の半導体装置の製造工程の一例について図12〜図28を参照して説明する。図12〜図28は、本実施の形態の半導体装置の製造工程中の要部断面図であり、上記図8にほぼ相当する断面図が示されている。なお、ここでは、本実施の形態の半導体装置の製造工程の好適な一例について説明するが、これに限定されず、種々変更可能である。
図29は、本実施の形態の半導体装置CPに対応する半導体チップCP1をパッケージ化した半導体装置(半導体パッケージ)PKG1の平面透視図であり、半導体装置PKG1を上面側から見て、封止部MRを透視した平面図(上面図)が示されている。図29では、封止部MRの外周位置を点線で示してある。図30および図31は、半導体装置PKG1の断面図であり、図29のD1−D1線の断面図が、図30にほぼ対応し、図29のD2−D2線の断面図が、図31にほぼ対応している。
図38は、本発明者が検討した第1検討例の半導体装置CP101の上面図であり、上記図1に相当するものである。図38では、LDMOSFET形成領域LR100を点線で示してある。図39は、第1検討例の半導体装置CP101の全体平面図であり、図38と同じ領域の平面図が示されているが、図39には、配線(すなわちソース配線M2S100およびゲート配線M2G100)の平面レイアウトが示されており、ソース配線M2S100およびゲート配線M2G100にハッチングを付してある。また、図39では、ソース用開口部OPS100およびゲート用開口部OPG100の位置を点線で示してある。図40は、第1検討例の半導体装置CP101の要部断面図であり、図38のB1−B1の断面図が図40にほぼ対応している。
本実施の形態の半導体装置CPは、半導体基板SUBと、半導体基板SUBの主面のLDMOSFET形成領域LR(第1MISFET形成領域)に形成され、互いに並列に接続される複数の単位LDMOSFET10a(単位MISFET素子)と、を有している。本実施の形態の半導体装置CPは、更に、半導体基板SUB上に形成され、第1配線層(配線M1)と第1配線層(配線M1)よりも上層の第2配線層(配線M2)とを有する配線構造と、半導体基板SUBの裏面に形成された裏面電極BEと、を有している。第1配線層は、上記配線M1に対応し、ソース配線M1S(第1ソース配線)およびゲート配線M1G(第1ゲート配線)を含んでおり、第2配線層は、上記配線M2に対応し、ソース配線M2S(第2ソース配線)およびゲート配線M2G(第2ゲート配線)を含んでいる。ソース配線M1Sおよびゲート配線M1Gのそれぞれの厚み(T1)は、ソース配線M2Sおよびゲート配線M2Gのそれぞれの厚み(T2)よりも小さい(薄い)。
図46および図47は、本実施の形態2の半導体装置(半導体チップ)CPの全体平面図であり、上記実施の形態1の上記図1および図2にそれぞれ対応するものである。図48は、本実施の形態2の半導体装置CPの要部断面図であり、図46のG−G線での断面図が、図48にほぼ対応している。
図51および図52は、本実施の形態3の半導体装置(半導体チップ)CPの全体平面図であり、上記実施の形態1の上記図1および図2にそれぞれに対応するものである。
上記実施の形態1〜3では、半導体装置(半導体チップ)CPにLDMOSFETを形成し、そのLDMOSFETのドレインを裏面電極BEに接続し、LDMOSFETのゲート電極をゲート配線でゲート用のパッドに引き上げ、LDMOSFETのソースをソース配線でソース用のパッドに引き上げている。
上記実施の形態1〜4では、半導体装置(半導体チップ)CPにLDMOSFETが形成され、LDMOSFETのゲート電極GEは、半導体基板SUB(エピタキシャル層EP)の主面上にゲート絶縁膜GIを介して形成されていた。
半導体基板と、
前記半導体基板の主面の第1MISFET形成領域に形成され、互いに並列に接続される複数の単位MISFET素子と、
前記半導体基板上に形成され、第1配線層と前記第1配線層よりも上層の第2配線層とを有する配線構造と、
前記半導体基板の前記主面とは反対側の裏面に形成された、ドレイン用の裏面電極と、
を有し、
前記複数の単位MISFET素子のそれぞれは、トレンチゲート型のMISFET素子であり、前記半導体基板の溝に埋め込まれたゲート電極と、前記半導体基板の表層部に形成されたソース領域とを有し、
前記配線構造の前記第1配線層は、第1ソース配線および第1ゲート配線を含み、
前記配線構造の前記第2配線層は、第2ソース配線および第2ゲート配線を含み、
前記第1ソース配線および前記第1ゲート配線のそれぞれの厚みは、前記第2ソース配線および前記第2ゲート配線のそれぞれの厚みよりも小さく、
前記複数の単位MISFET素子のそれぞれの前記ソース領域は、前記第1ソース配線および前記第2ソース配線を介して互いに電気的に接続され、
前記複数の単位MISFET素子のそれぞれの前記ゲート電極は、前記第1ゲート配線を介して互いに電気的に接続され、かつ、前記第1ゲート配線を介して前記第2ゲート配線に電気的に接続され、
前記ゲート電極の上方に前記第1ゲート配線が延在している、半導体装置。
付記1に記載の半導体装置において、
前記第1MISFET形成領域の上方において、前記第1ゲート配線は、前記ゲート電極の延在方向である第1方向に延在する部分と、前記第1方向と交差する第2方向に延在する部分とを一体的に有し、
前記第1ゲート配線の前記第1方向に延在する部分は、前記ゲート電極の上方を前記第1方向に延在している、半導体装置。
付記2に記載の半導体装置において、
前記第1ソース配線は、前記第1ゲート配線を間に挟んで、複数の孤立ソース配線に分割されており、
前記複数の単位MISFET素子のそれぞれの前記ソース領域の上方に、前記孤立ソース配線が配置され、
前記複数の孤立ソース配線を覆うように、前記第2ソース配線が配置され、
前記複数の孤立ソース配線は、前記第2ソース配線を介して互いに電気的に接続されている、半導体装置。
付記3に記載の半導体装置において、
前記複数の孤立ソース配線のそれぞれは、平面視で前記第1ゲート配線に囲まれている、半導体装置。
付記1に記載の半導体装置において、
前記第2ソース配線により、ソース用のパッドが形成され、
前記第2ゲート配線により、ゲート用のパッドが形成されている、半導体装置。
10a,100a 単位LDMOSFET
10b 単位トランジスタセル
AR 活性領域
BE 裏面電極
CP,CP101,CP102,CP103 半導体装置
CP1,CP2,CP3 半導体チップ
DP1,DP2,DP3 ダイパッド
DR1 n型低濃度ドレイン領域
DR2 n+型高濃度ドレイン領域
EP エピタキシャル層
FP フィールドプレート電極
GE,GE2 ゲート電極
GE1 連結部
GI,GI2 ゲート絶縁膜
IL1,IL2,IL3 絶縁膜
LD,LD1,LD2,LD3,LD4,LD5,LD6,LD7,LD8 リード
LDR 連結部
LR,LR100 LDMOSFET形成領域
LR2 MOSFET形成領域
M1,M2 配線
M1D,M2D ドレイン配線
M1G,M2G,M2G100 ゲート配線
M2G1,M2G101 配線部
M2G2,M2G102 パッド部
M2G3 配線部
M1S,M2S,M2S1,M2S2 ソース配線
M2G103,M2G103a,M2G103b,M2G103c 配線部
M2S100,M2S101,M2S102 ソース配線
M2S103,M2S104,M2S105,M2S106 ソース配線
MP1,MP2,MP3 金属板
MR 封止部
MRa 上面
MRb 裏面
NS1,NS2 n+型半導体領域
OP 開口部
OPD ドレイン用開口部
OPG,OPG100 ゲート用開口部
OPS,OPS100 ソース用開口部
PA 絶縁膜
PD3,PDD,PDG,PDS,PDS1,PDS2 パッド
PDS100,PDS101,PDS102,PDS103 パッド
PDS104,PDS105,PDS106 パッド
PGD,PGF,PGG,PGG2,PGS,PGS2 プラグ
PKG1,PKG1a 半導体装置
PR p型半導体層
PR2 p型半導体領域
PS,PS1,PS2 p+型半導体領域
PW p型半導体領域
RG1,RG2 領域
SB 基板本体
SD2,SD3 接着層
SL 金属シリサイド層
SR n+型ソース領域
SR2 n+型半導体領域
ST 素子分離領域
SUB 半導体基板
SW サイドウォールスペーサ
THD,THG,THS スルーホール
TL プラグ
TL1 窒化チタン膜
TL2 タングステン膜
TR,TR2 溝
WA ワイヤ(ボンディングワイヤ)
Claims (20)
- 半導体基板と、
前記半導体基板の主面の第1MISFET形成領域に形成され、互いに並列に接続される複数の単位MISFET素子と、
前記半導体基板上に形成され、第1配線層と前記第1配線層よりも上層の第2配線層とを有する配線構造と、
前記半導体基板の前記主面とは反対側の裏面に形成された裏面電極と、
を有し、
前記複数の単位MISFET素子のそれぞれは、前記半導体基板に形成されたソース領域およびドレイン領域と、前記ソース領域と前記ドレイン領域との間の前記半導体基板上にゲート絶縁膜を介して形成されたゲート電極と、を有し、
前記配線構造の前記第1配線層は、第1ソース配線および第1ゲート配線を含み、
前記配線構造の前記第2配線層は、第2ソース配線および第2ゲート配線を含み、
前記第1ソース配線および前記第1ゲート配線のそれぞれの厚みは、前記第2ソース配線および前記第2ゲート配線のそれぞれの厚みよりも小さく、
前記複数の単位MISFET素子のそれぞれの前記ドレイン領域は、前記半導体基板の溝に埋め込まれた導電性のプラグを介して前記裏面電極と電気的に接続されることにより、互いに電気的に接続され、
前記複数の単位MISFET素子のそれぞれの前記ソース領域は、前記第1ソース配線および前記第2ソース配線を介して互いに電気的に接続され、
前記複数の単位MISFET素子のそれぞれの前記ゲート電極は、前記第1ゲート配線を介して互いに電気的に接続され、かつ、前記第1ゲート配線を介して前記第2ゲート配線に電気的に接続され、
前記プラグの上方に前記第1ゲート配線が延在している、半導体装置。 - 請求項1記載の半導体装置において、
前記プラグの上方を、前記第1ゲート配線が、前記ゲート電極の延在方向である第1方向に延在している、半導体装置。 - 請求項2記載の半導体装置において、
前記プラグは、前記ドレイン領域を間に挟んで隣り合う前記ゲート電極の間を、前記第1方向に延在している、半導体装置。 - 請求項3記載の半導体装置において、
前記第1MISFET形成領域の上方において、前記第1ゲート配線は、前記第1方向に延在する部分と、前記第1方向と交差する第2方向に延在する部分とを一体的に有し、
前記第1ゲート配線の前記第1方向に延在する部分は、前記プラグの上方を前記第1方向に延在している、半導体装置。 - 請求項4記載の半導体装置において、
前記第1ソース配線は、前記第1ゲート配線を間に挟んで、複数の孤立ソース配線に分割されており、
前記複数の単位MISFET素子のそれぞれの前記ソース領域の上方に、前記孤立ソース配線が配置され、
前記複数の孤立ソース配線を覆うように、前記第2ソース配線が配置され、
前記複数の孤立ソース配線は、前記第2ソース配線を介して互いに電気的に接続されている、半導体装置。 - 請求項5記載の半導体装置において、
前記複数の孤立ソース配線のそれぞれは、平面視で前記第1ゲート配線に囲まれている、半導体装置。 - 請求項6記載の半導体装置において、
前記孤立ソース配線は、前記ゲート電極の上方にも延在している、半導体装置。 - 請求項7記載の半導体装置において、
前記複数の単位MISFET素子のそれぞれは、フィールドプレート電極を更に有し、
前記孤立ソース配線は前記フィールドプレート電極上にも延在し、
前記フィールドプレート電極は、前記孤立ソース配線に電気的に接続されている、半導体装置。 - 請求項8記載の半導体装置において、
前記フィールドプレート電極は、前記ドレイン領域の一部上から前記ゲート電極の一部上にかけて絶縁膜を介して延在している、半導体装置。 - 請求項6記載の半導体装置において、
前記第1ゲート配線は、前記第1MISFET形成領域の外周に沿って延在する部分を有し、
前記第2ゲート配線は、前記第1MISFET形成領域の外周に沿って延在する部分を有し、
前記第1MISFET形成領域の外周に沿って延在する部分の前記第1ゲート配線は、前記第1MISFET形成領域の外周に沿って延在する部分の前記第2ゲート配線と平面視で重なっている、半導体装置。 - 請求項1記載の半導体装置において、
前記第2ソース配線により、ソース用のパッドが形成され、
前記第2ゲート配線により、ゲート用のパッドが形成されている、半導体装置。 - 請求項1記載の半導体装置において、
前記配線構造の前記第1配線層および前記第2配線層は、前記複数の単位MISFET素子の前記ドレイン領域に接続される配線は有していない、半導体装置。 - 請求項1記載の半導体装置において、
前記単位MISFET素子は、単位LDMOSFET素子である、半導体装置。 - 請求項1記載の半導体装置において、
前記プラグは、前記半導体基板の前記溝に埋め込まれた金属膜からなる、半導体装置。 - 請求項1記載の半導体装置において、
前記第1ソース配線は、前記プラグの上方には配置されていない、半導体装置。 - 半導体基板と、
前記半導体基板の主面の第1MISFET形成領域に形成され、互いに並列に接続される複数の単位MISFET素子と、
前記半導体基板上に形成され、第1配線層と前記第1配線層よりも上層の第2配線層とを有する配線構造と、
前記半導体基板の前記主面とは反対側の裏面に形成された裏面電極と、
を有し、
前記複数の単位MISFET素子のそれぞれは、前記半導体基板に形成されたソース領域およびドレイン領域と、前記ソース領域と前記ドレイン領域との間の前記半導体基板上にゲート絶縁膜を介して形成されたゲート電極と、を有し、
前記配線構造の前記第1配線層は、第1ドレイン配線および第1ゲート配線を含み、
前記配線構造の前記第2配線層は、第2ドレイン配線および第2ゲート配線を含み、
前記第1ドレイン配線および前記第1ゲート配線のそれぞれの厚みは、前記第2ドレイン配線および前記第2ゲート配線のそれぞれの厚みよりも小さく、
前記複数の単位MISFET素子のそれぞれの前記ソース領域は、前記半導体基板の溝に埋め込まれた導電性のプラグを介して前記裏面電極と電気的に接続されることにより、互いに電気的に接続され、
前記複数の単位MISFET素子のそれぞれの前記ドレイン領域は、前記第1ドレイン配線および前記第2ドレイン配線を介して互いに電気的に接続され、
前記複数の単位MISFET素子のそれぞれの前記ゲート電極は、前記第1ゲート配線を介して互いに電気的に接続され、かつ、前記第1ゲート配線を介して前記第2ゲート配線に電気的に接続され、
前記プラグの上方に前記第1ゲート配線が延在している、半導体装置。 - 請求項16記載の半導体装置において、
前記第1MISFET形成領域の上方において、前記第1ゲート配線は、前記ゲート電極の延在方向である第1方向に延在する部分と、前記第1方向と交差する第2方向に延在する部分とを一体的に有し、
前記第1ゲート配線の前記第1方向に延在する部分は、前記プラグの上方を前記第1方向に延在している、半導体装置。 - 請求項17記載の半導体装置において、
前記第1ドレイン配線は、前記第1ゲート配線を間に挟んで、複数の孤立ドレイン配線に分割されており、
前記複数の単位MISFET素子のそれぞれの前記ドレイン領域の上方に、前記孤立ドレイン配線が配置され、
前記複数の孤立ドレイン配線を覆うように、前記第2ドレイン配線が配置され、
前記複数の孤立ドレイン配線は、前記第2ドレイン配線を介して互いに電気的に接続されている、半導体装置。 - 請求項18記載の半導体装置において、
前記複数の孤立ドレイン配線のそれぞれは、平面視で前記第1ゲート配線に囲まれている、半導体装置。 - 請求項16記載の半導体装置において、
前記第2ドレイン配線により、ドレイン用のパッドが形成され、
前記第2ゲート配線により、ゲート用のパッドが形成されている、半導体装置。
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US9397160B2 (en) | 2016-07-19 |
CN104659026A (zh) | 2015-05-27 |
US20150380487A1 (en) | 2015-12-31 |
CN104659026B (zh) | 2019-02-15 |
JP6219140B2 (ja) | 2017-10-25 |
US9142555B2 (en) | 2015-09-22 |
US20150145025A1 (en) | 2015-05-28 |
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