JP2015046643A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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Abstract
【解決手段】半導体装置10は、配線基板11と第1の半導体チップ12と第2の半導体チップ13とを有する。配線基板は、第1の表面と第1の表面に形成された第1の凹所116とを含む。配線基板の第1の凹所が形成された部分は配線基板の周辺部分よりも薄い。第1の半導体チップは、配線基板の第1の表面上に搭載され、一つの縁が第1の凹所に隣接して配置される。第2の半導体チップは、第1の半導体チップ上に積層され、第1の半導体チップの縁から延びたオーバーハング部を形成する。第2の半導体チップは、配線基板に対向する第1の主面と、第1の主面の反対側の第2の主面と、第2の主面に形成された電極パッド131とを含む。電極パッドは、配線基板の第1の凹所と垂直方向に並んでいる。
【選択図】図1
Description
図1及び図2は、それぞれ、本発明の第1の実施の形態に係る半導体装置の概略構成を示す断面図及び平面図である。なお、図2の平面図では封止樹脂(図1の15)が省略されている。
図9及び図10は、それぞれ、本発明の第2の実施の形態に係る半導体装置10−1の概略構成を示す断面図及び平面図である。ここで、第1の実施の形態に係る半導体装置10と同一の部材には同一の参照符号を付与し、その説明を省略する。
図11は、本発明の第3の実施の形態に係る半導体装置10−2の概略構成を示す断面図である。また、図12は、半導体装置10−2の製造に用いられる配線母基板30−2の平面図である。
図13は、本発明の第4の実施の形態に係る半導体装置10−3の概略構成を示す平面図である。
11,11−1,11−2,11−3 配線基板
12 第1の半導体チップ
13,13−3 第2の半導体チップ
14 ワイヤ
15 封止樹脂
16 半田ボール
111 絶縁基材
112,112−1,112−2,112−3 絶縁膜
113 接続パッド
114 ランド部
115,116,116−1,116−2,116−3,116−4 開口部
121 電極パッド
122 接着部材
131 電極パッド
132,132−1,132−2 オーバーハング部
133 接着部材
30,30−2 配線母基板
31 位置決め穴
32 枠部
33 製品形成部
34 ダイシングライン
51 ダイシングテープ
71 上型
72 下型
73 キャビティ
74 プランジャー
75 原料タブレット
76 カル
77 ランナ
78 ゲート
79 溶融樹脂
140 バンプ
141 アンダーフィル
Claims (13)
- 第1の表面と前記第1の表面に形成された第1の凹所とを含む配線基板であって、前記配線基板の前記第1の凹所の形成された部分が前記配線基板の周辺部分よりも薄く形成されている前記配線基板と、
前記配線基板の前記第1の表面上に搭載された第1の半導体チップであって、前記第1の半導体チップの一つの縁が前記第1の凹所に隣接して配置された前記第1の半導体チップと、
前記第1の半導体チップ上に積層された第2の半導体チップであって、前記第1の半導体チップの前記縁から延びたオーバーハング部を形成する前記第2の半導体チップと、を有し、
前記第2の半導体チップは、前記配線基板に対向する第1の主面と、前記第1の主面の反対側の第2の主面と、前記第2の主面に形成された電極パッドとを含み、
前記電極パッドは、前記配線基板の前記第1の凹所と垂直方向に並んでいる、
ことを特徴とする半導体装置。 - 前記第2の半導体チップの前記オーバーハング部は、前記配線基板の前記第1の凹所と実質的にサイズが等しいこと特徴とする請求項1に記載の半導体装置。
- 前記第2の半導体チップの前記オーバーハング部は、前記配線基板の前記第1の凹所と垂直方向に並んでいること特徴とする請求項1に記載の半導体装置。
- 前記配線基板の前記第1の凹所は、前記第2の半導体チップの前記オーバーハング部よりもサイズが大きいことを特徴とする請求項1に記載の半導体装置。
- 前記配線基板は、基材と前記基材上に形成された絶縁膜とを含み、前記第1の凹所は前記絶縁膜に形成されて前記基材の表面を露出させることを特徴とする請求項1に記載の半導体装置。
- 前記配線基板の前記第1の表面上に形成されて前記第1の半導体チップと前記第2の半導体チップを覆う封止樹脂をさらに有し、前記第1の凹所が前記封止樹脂によって埋められていることを特徴とする請求項1に記載の半導体装置。
- 前記第1の凹所は、前記配線基板の第1の縁と平行に形成され、かつ、前記第1の縁に直交する前記配線基板の第2の縁から前記第1の縁に直交する前記配線基板の第3の縁まで連続して形成されていることを特徴とする請求項1に記載の半導体装置。
- 前記配線基板は、前記第1の表面に形成された第2の凹所と、前記第2の凹所に形成された接続パッドとを含み、
前記第2の凹所は、平面視で、その位置と前記第1の半導体チップとの間に前記第1の凹所が挟まれる位置に配置され、
前記接続パッドは、前記第2半導体チップの電極パッドに電気的に接続されていることを特徴とする請求項1に記載の半導体装置。 - 前記第1の半導体チップは、前記配線基板に対向する第3の主面と、前記第3の主面に形成された第2の電極パッドとを含むことを特徴とする請求項8に記載の半導体装置。
- 基材と前記基材上に形成された絶縁膜とを有する配線基板であって、前記絶縁膜が互いに離れた第1及び第2の開口を含み、前記第1の開口によって前記絶縁膜から露出するように前記基材上に形成された複数の接続パッドを含む前記配線基板と、
前記配線基板上に搭載された第1の半導体チップであって、前記第1の半導体チップが平面視でその位置と前記第1の開口との間に前記第2の開口が挟まれる位置に配置されており、前記絶縁膜が前記第1の半導体チップと前記基材との間に存在している前記第1の半導体チップと、
第2の半導体チップであって、前記第2の半導体チップの一部が前記絶縁膜の前記第2開口と垂直方向に並ぶように前記第1の半導体チップ上に積層されている第2の半導体チップと、
を有することを特徴とする半導体装置。 - 前記絶縁膜の前記第2の開口は、前記第2の半導体チップの前記一部よりもサイズが大きいことを特徴とする請求項10に記載の半導体装置。
- 前記第2の開口は前記配線基板の前記基材の縁の一つに達していることを特徴とする請求項10に記載の半導体装置。
- 前記第2の半導体チップは、前記配線基板に対向する第1の主面と、前記第1の主面の反対側の第2の主面と、前記第2の主面上に形成された複数の電極パッドとを含み、前記複数の電極バッドは前記第2の開口と垂直方向に並び、前記複数の電極パッドの各々はボンディングワイヤを介して前記複数の接続パッドのいずれかに電気的に接続されていることを特徴とする請求項10に記載の半導体装置。
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JP2004273963A (ja) * | 2003-03-12 | 2004-09-30 | Renesas Technology Corp | 半導体装置 |
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JP2008147226A (ja) * | 2006-12-06 | 2008-06-26 | Toppan Printing Co Ltd | 半導体装置及びその製造方法 |
JP2009152262A (ja) * | 2007-12-19 | 2009-07-09 | Renesas Technology Corp | 半導体装置およびその製造方法 |
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JP2004273963A (ja) * | 2003-03-12 | 2004-09-30 | Renesas Technology Corp | 半導体装置 |
JP2005340415A (ja) * | 2004-05-26 | 2005-12-08 | Sony Corp | 半導体パッケージ及びその製造方法 |
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