JP2014517546A - 構造化された焼結結合層の製造方法及び構造化された焼結結合層を備えている半導体素子 - Google Patents
構造化された焼結結合層の製造方法及び構造化された焼結結合層を備えている半導体素子 Download PDFInfo
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- JP2014517546A JP2014517546A JP2014516395A JP2014516395A JP2014517546A JP 2014517546 A JP2014517546 A JP 2014517546A JP 2014516395 A JP2014516395 A JP 2014516395A JP 2014516395 A JP2014516395 A JP 2014516395A JP 2014517546 A JP2014517546 A JP 2014517546A
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Abstract
Description
本発明が基礎とする着想は、基板とチップとの間に良好な電気的及び熱的な結合を確立し、更にはチップ内の機械的な応力も低減する焼結結合部を基板とチップとの間に形成することである。このことは、基板とチップとの間においてコンタクト面上に構造化されて位置決めされる複数の焼結要素から成る焼結層によって解決される。コンタクト面の中心における焼結要素の面占有率が高くなっていることによって、チップの動作時に一般的に高い温度が発生する領域において、良好な熱伝性及び導電性を保証することができる。コンタクト面の縁部においては、焼結要素の面占有率が中心における面占有率よりも低いので、それにより縁部領域では焼結時に各焼結要素に作用する圧縮圧力が中心領域よりも著しく高くなっており、それによって縁部領域における焼結結合部の信頼性が高められている。
Claims (10)
- 焼結層(12)の製造方法において、
前記焼結層(12)を形成する出発材料から成る複数の焼結要素(22a,22b,22c)を構造化して、基板(11)の主表面(11a)のコンタクト面(21)上に被着させるステップと、
前記基板(11)と接続すべきチップ(13)を前記焼結要素(22a,22b,22c)の上に配置するステップと、
前記基板(11)と前記チップ(13)を接続し、且つ前記コンタクト面(21)の内側に延在する、構造化された焼結層(12)を形成するために前記焼結要素(22a,22b,22c)を加熱及び圧縮するステップとを備えており、
前記コンタクト面(21)の中心領域(21a)における、前記基板(11)上の焼結要素(22a,22b,22c)の面占有率は、前記コンタクト面(21)の縁部領域(21c)における焼結要素(22a,22b,22c)の面占有率よりも大きく、
各焼結要素(22a,22b,22c)からは、前記基板(11)の前記主表面(11a)に対して水平方向に延在している少なくとも一つの通路(23)が前記コンタクト面(21)の縁部まで形成されていることを特徴とする、焼結層(12)の製造方法。 - 前記出発材料は、マイクロ粒子及び/又はナノ粒子から成るものであり、且つ、主成分として銀を含有している焼結ペーストである、請求項1に記載の方法。
- 前記コンタクト面(21)の前記縁部領域(21c)における焼結要素(22a,22b,22c)の数は、前記コンタクト面(21)の中心領域(21a)における焼結要素(22a,22b,22c)の数よりも多い、請求項1又は2に記載の方法。
- 前記中心領域(21a)と前記縁部領域(21c)との間の前記コンタクト面(21)の領域(21b)における、前記基板(11)上の焼結要素(22a,22b,22c)の面占有率は、前記コンタクト面(21)の前記中心領域(21a)における面占有率と、前記縁部領域(21c)における面占有率との間にある、請求項1乃至3のいずれか一項に記載の方法。
- 前記コンタクト面(21)の縁部は、水平方向において、前記基板(11)の前記主表面(11a)に沿って、前記チップ(13)のエッジから所定の長さだけ離隔されて設けられている、請求項1乃至4のいずれか一項に記載の方法。
- 半導体素子(10)において、
該半導体素子(10)は、
主表面(11a)を備えている基板(11)と、
前記基板(11)の前記主表面(11a)上に配置されている半導体チップ(13)と、
前記基板(11)と前記半導体チップ(13)との間において前記主表面(11a)のコンタクト面(21)上に配置されており、且つ、前記半導体チップ(13)を前記基板(11)に接続させる、構造化された焼結層(12)とを有しており、
前記焼結層(12)は複数の焼結要素(22a,22b,22c)を含んでおり、前記コンタクト面(21)の中心領域(21a)における、前記基板(11)上の焼結要素(22a,22b,22c)の面占有率は、前記コンタクト面(21)の縁部領域(21c)における焼結要素(22a,22b,22c)の面占有率よりも大きく、
各焼結要素(22a,22b,22c)からは、前記基板(11)の前記主表面(11a)に対して水平方向に延在している少なくとも一つの通路(23)が、前記基板(11)と前記半導体チップ(13)との間において前記コンタクト面(21)の縁部まで形成されている、ことを特徴とする半導体素子(10)。 - 前記コンタクト面(21)の前記縁部領域(21c)における焼結要素(22a,22b,22c)の数は、前記コンタクト面(21)の中心領域(21a)における焼結要素(22a,22b,22c)の数よりも多い、請求項6に記載の半導体素子(10)。
- 前記中心領域(21a)と前記縁部領域(21c)との間の前記コンタクト面(21)の領域(21b)における、前記基板(11)上の焼結要素(22a,22b,22c)の面占有率は、前記コンタクト面(21)の前記中心領域(21a)における面占有率と、前記縁部領域(21c)における面占有率との間にある、請求項6又は7に記載の半導体素子(10)。
- 前記半導体チップ(13)にはパワートランジスタ又はパワーダイオード又はサイリスタが含まれ、
前記基板(11)にはDBC基板、IMS(Insulated Metal Substrate)基板、PCB(Printed Circuit Board)基板、AMB(Active Metal Brazing)基板又はセラミック性の単層又は多層の基板が含まれる、請求項6乃至8のいずれか一項に記載の半導体素子(10)。 - 前記コンタクト面(21)の前記中心領域(21a)における焼結要素(22a)の水平方向の寸法は、前記コンタクト面(21)の前記縁部領域(21c)における焼結要素(22c)の水平方向の寸法よりも大きい、請求項6乃至9のいずれか一項に記載の半導体素子(10)。
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JP2009054893A (ja) * | 2007-08-28 | 2009-03-12 | Panasonic Electric Works Co Ltd | 発光装置 |
EP2075835A2 (de) * | 2007-12-28 | 2009-07-01 | Robert Bosch Gmbh | Diode mit Vorrichtungen zur Reduktion der mechanischen Spannung |
JP2011071301A (ja) * | 2009-09-25 | 2011-04-07 | Honda Motor Co Ltd | 金属ナノ粒子を用いた接合方法及び接合体 |
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JP2014029964A (ja) * | 2012-07-31 | 2014-02-13 | Mitsubishi Materials Corp | 接合体の製造方法、パワーモジュールの製造方法、及びパワーモジュール |
JP2015188026A (ja) * | 2014-03-27 | 2015-10-29 | 三菱電機株式会社 | 電力用半導体装置、および電力用半導体装置の製造方法 |
JP2019079883A (ja) * | 2017-10-23 | 2019-05-23 | 日立化成株式会社 | 部材接続方法 |
JP7127269B2 (ja) | 2017-10-23 | 2022-08-30 | 昭和電工マテリアルズ株式会社 | 部材接続方法 |
Also Published As
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WO2013004543A1 (de) | 2013-01-10 |
CN103635997B (zh) | 2017-09-01 |
DE102011078582A1 (de) | 2013-01-10 |
US20140225274A1 (en) | 2014-08-14 |
WO2013004543A9 (de) | 2013-03-14 |
US9887173B2 (en) | 2018-02-06 |
EP2729965B1 (de) | 2020-08-05 |
JP5762632B2 (ja) | 2015-08-12 |
EP2729965A1 (de) | 2014-05-14 |
CN103635997A (zh) | 2014-03-12 |
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