JP2014187194A - 半導体装置の製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 29
- 239000007772 electrode material Substances 0.000 claims abstract description 59
- 238000005530 etching Methods 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 230000003071 parasitic effect Effects 0.000 abstract description 17
- 238000009413 insulation Methods 0.000 abstract 4
- 239000010410 layer Substances 0.000 description 83
- 239000012535 impurity Substances 0.000 description 11
- 230000000052 comparative effect Effects 0.000 description 7
- 239000011229 interlayer Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 229920005591 polysilicon Polymers 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 239000000758 substrate Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/402—Field plates
- H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
- H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
Abstract
【解決手段】実施形態に係る半導体装置の製造方法は、半導体層にトレンチを形成し、前記トレンチの内面を覆う第1絶縁膜を形成し、前記トレンチの内部を埋め込み、前記半導体の上面を覆う電極材料を形成し、前記電極材料の前記トレンチの内部を埋め込んだ部分および開口を覆う部分を残して、前記電極材料を選択的に除去する。そして、前記トレンチ上部の内面を覆う前記第1絶縁膜を除去し、前記電極材料の前記トレンチの開口を覆う部分および前記トレンチに埋め込まれた部分をエッチバックして前記トレンチの下部に第1電極を形成し、前記トレンチ上部の内面を覆う第2絶縁膜と、前記トレンチ上部に露出した前記第1電極の端部を覆う第3絶縁膜と、を形成し、前記第1電極の上に第2電極を形成する。
【選択図】図1
Description
また、FP電極23は、その上端23aがFP絶縁膜25よりも上方に突出するように設けられる。さらに、FP電極23の上端23aは、絶縁膜31(第3絶縁膜)に覆われる。そして、FP電極23とゲート電極27との間は、絶縁膜31により絶縁される。
Cgs=Cgs1+Cgs2+Cgs3
である。Cgs1は、ゲート電極27とベース層15との間の寄生容量である。ベース層15は、コンタクト層19を介してソース電極35と電気的に接続されている。Cgs2は、ゲート電極27とFP電極23との間の寄生容量である。FP電極23とソース電極35は、図示しない部分で電気的に接続される。そして、Cgs3は、ゲート電極27とソース電極35との間の寄生容量である。
Claims (5)
- 半導体層の上面から下面方向にトレンチを形成し、
前記トレンチの内面を覆う第1絶縁膜を形成し、
前記トレンチの内部を埋め込み、前記半導体の上面を覆う電極材料を形成し、
前記電極材料の前記トレンチの内部を埋め込んだ部分および前記トレンチの開口を覆う部分を残して前記電極材料を選択的に除去し、
前記トレンチ上部を覆う前記第1絶縁膜を除去し、
前記電極材料の前記トレンチの開口を覆う部分および前記トレンチに埋め込まれた部分をエッチバックして前記トレンチの下部に第1電極を形成し、
前記トレンチ上部の内面を覆う第2絶縁膜と、前記トレンチ上部において前記第1絶縁膜から露出した前記第1電極の端部を覆う第3絶縁膜と、を形成し、
前記第1電極の上に前記第3絶縁膜を介して第2電極を形成する半導体装置の製造方法。 - 前記半導体層を熱酸化して前記第2絶縁膜を形成し、
前記第1電極を熱酸化して前記第3絶縁膜を形成する請求項1記載の半導体装置の製造方法。 - 前記半導体層を熱酸化して前記第1絶縁膜を形成する請求項1または2に記載の半導体装置の製造方法。
- 前記電極材料は、多結晶シリコンである請求項1〜3のいずれか1つに記載の半導体装置の製造方法。
- 前記電極材料の前記トレンチの開口を覆う部分の幅は、前記開口の幅と同じか、または、それよりも広い請求項1〜4のいずれか1つに記載の半導体装置の製造方法。
Priority Applications (2)
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JP2013061119A JP5784665B2 (ja) | 2013-03-22 | 2013-03-22 | 半導体装置の製造方法 |
US14/023,235 US8969157B2 (en) | 2013-03-22 | 2013-09-10 | Method of manufacturing semiconductor device having field plate electrode |
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JP2013061119A JP5784665B2 (ja) | 2013-03-22 | 2013-03-22 | 半導体装置の製造方法 |
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JP2014187194A true JP2014187194A (ja) | 2014-10-02 |
JP5784665B2 JP5784665B2 (ja) | 2015-09-24 |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021034444A (ja) * | 2019-08-20 | 2021-03-01 | 株式会社東芝 | 半導体装置 |
JP2021093392A (ja) * | 2019-12-06 | 2021-06-17 | 株式会社東芝 | 半導体装置及びその製造方法 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6400545B2 (ja) | 2015-09-11 | 2018-10-03 | 株式会社東芝 | 半導体装置 |
EP3142149A1 (en) * | 2015-09-11 | 2017-03-15 | Nexperia B.V. | A semiconductor device and a method of making a semiconductor device |
CN105529273B (zh) * | 2016-01-15 | 2018-08-21 | 上海华虹宏力半导体制造有限公司 | 沟槽栅功率器件的制造方法 |
JP6649216B2 (ja) * | 2016-09-16 | 2020-02-19 | 株式会社東芝 | 半導体装置およびその製造方法 |
JP6744270B2 (ja) * | 2017-09-20 | 2020-08-19 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP7106476B2 (ja) * | 2019-03-19 | 2022-07-26 | 株式会社東芝 | 半導体装置およびその製造方法 |
CN111816709B (zh) * | 2020-09-03 | 2021-06-11 | 江苏应能微电子有限公司 | 一种屏蔽闸沟槽式功率金属氧化物半导体场效晶体管 |
CN112802892A (zh) * | 2021-01-06 | 2021-05-14 | 华虹半导体(无锡)有限公司 | Sgt结构及其制作方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2007535822A (ja) * | 2004-04-30 | 2007-12-06 | シリコニックス インコーポレーテッド | 埋込みソース電極を含むスーパートレンチmosfetおよびそれを製造する方法 |
US20100181641A1 (en) * | 2009-01-16 | 2010-07-22 | Infineon Technologies Austria Ag | Semiconductor device and method for manufacturing |
JP2013508984A (ja) * | 2009-10-21 | 2013-03-07 | ヴィシェイ−シリコニックス | 曲線状のゲート酸化物プロファイルを有するスプリットゲート半導体素子 |
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WO2005065385A2 (en) | 2003-12-30 | 2005-07-21 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
JP5183959B2 (ja) | 2007-04-23 | 2013-04-17 | 新日本無線株式会社 | Mosfet型半導体装置の製造方法 |
JP2011199109A (ja) | 2010-03-23 | 2011-10-06 | Renesas Electronics Corp | パワーmosfet |
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2013
- 2013-03-22 JP JP2013061119A patent/JP5784665B2/ja not_active Expired - Fee Related
- 2013-09-10 US US14/023,235 patent/US8969157B2/en not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2007535822A (ja) * | 2004-04-30 | 2007-12-06 | シリコニックス インコーポレーテッド | 埋込みソース電極を含むスーパートレンチmosfetおよびそれを製造する方法 |
US20100181641A1 (en) * | 2009-01-16 | 2010-07-22 | Infineon Technologies Austria Ag | Semiconductor device and method for manufacturing |
JP2013508984A (ja) * | 2009-10-21 | 2013-03-07 | ヴィシェイ−シリコニックス | 曲線状のゲート酸化物プロファイルを有するスプリットゲート半導体素子 |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2021034444A (ja) * | 2019-08-20 | 2021-03-01 | 株式会社東芝 | 半導体装置 |
JP7252860B2 (ja) | 2019-08-20 | 2023-04-05 | 株式会社東芝 | 半導体装置 |
JP2021093392A (ja) * | 2019-12-06 | 2021-06-17 | 株式会社東芝 | 半導体装置及びその製造方法 |
JP7319491B2 (ja) | 2019-12-06 | 2023-08-02 | 株式会社東芝 | 半導体装置及びその製造方法 |
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US8969157B2 (en) | 2015-03-03 |
US20140287574A1 (en) | 2014-09-25 |
JP5784665B2 (ja) | 2015-09-24 |
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