JP2014168007A - 配線基板およびその製造方法 - Google Patents
配線基板およびその製造方法 Download PDFInfo
- Publication number
- JP2014168007A JP2014168007A JP2013039725A JP2013039725A JP2014168007A JP 2014168007 A JP2014168007 A JP 2014168007A JP 2013039725 A JP2013039725 A JP 2013039725A JP 2013039725 A JP2013039725 A JP 2013039725A JP 2014168007 A JP2014168007 A JP 2014168007A
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- resin layer
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- thermal expansion
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- 238000004519 manufacturing process Methods 0.000 title abstract description 23
- 229920005989 resin Polymers 0.000 claims abstract description 127
- 239000011347 resin Substances 0.000 claims abstract description 127
- 239000004744 fabric Substances 0.000 claims abstract description 65
- 239000011521 glass Substances 0.000 claims abstract description 65
- 239000004020 conductor Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 34
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 69
- 229910052802 copper Inorganic materials 0.000 claims description 40
- 239000010949 copper Substances 0.000 claims description 40
- 239000011889 copper foil Substances 0.000 claims description 29
- 238000010030 laminating Methods 0.000 claims description 11
- 238000005530 etching Methods 0.000 claims description 6
- 239000011888 foil Substances 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 6
- 238000009413 insulation Methods 0.000 abstract description 3
- 238000007747 plating Methods 0.000 description 38
- 238000000034 method Methods 0.000 description 15
- 229920001187 thermosetting polymer Polymers 0.000 description 14
- 239000003822 epoxy resin Substances 0.000 description 11
- 229920000647 polyepoxide Polymers 0.000 description 11
- 229910000679 solder Inorganic materials 0.000 description 7
- 238000005553 drilling Methods 0.000 description 6
- 230000009477 glass transition Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000005498 polishing Methods 0.000 description 5
- 230000008602 contraction Effects 0.000 description 3
- 239000000654 additive Substances 0.000 description 2
- 238000003754 machining Methods 0.000 description 2
- 239000004593 Epoxy Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/036—Multilayers with layers of different types
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0313—Organic insulating material
- H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
- H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/06—Thermal details
- H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4661—Adding a circuit layer by direct wet plating, e.g. electroless plating; insulating materials adapted therefor
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49128—Assembling formed circuit to base
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
製造中および製造後における反りの発生が小さく、それにより製造が容易であるとともに、半導体素子Sを正常に搭載することが可能な配線基板を提供すること。
【解決手段】
ガラスクロス入り絶縁樹脂層11a,11bから成る絶縁板11の両面に配線導体12が形成されたコア基板10の片面または両面に、絶縁板11よりも熱膨張係数が大きな絶縁樹脂層21の表面に配線導体22が形成されたビルドアップ層20を、コア基板10の両面で異なる層数積層して成る配線基板Aであって、絶縁板11は、ビルドアップ層20の層数が多い面側の熱膨張係数が反対面側の熱膨張係数よりも小さい。
【選択図】図1
Description
11 絶縁板
11a 第1のガラスクロス入り絶縁樹脂層
11aP 片面銅張板
11b 第2のガラスクロス入り絶縁樹脂層
11bP プリプレグ
12 配線導体
12F 銅箔
20 ビルドアップ層
21 絶縁樹脂層
22 配線導体
Claims (2)
- ガラスクロス入り絶縁樹脂層から成る絶縁板の両面に配線導体が形成されたコア基板の片面または両面に、前記絶縁板よりも熱膨張係数が大きな絶縁樹脂層の表面に配線導体が形成されたビルドアップ層を、前記コア基板の両面で異なる層数積層して成る配線基板であって、前記絶縁板は、前記ビルドアップ層の層数が多い面側の熱膨張係数が反対面側の熱膨張係数よりも小さいことを特徴とする配線基板。
- 第1の熱膨張係数を有する第1のガラスクロス入り絶縁樹脂層の第1の片面に第1の銅箔が張り付けられた片面銅張板と、硬化後の熱膨張係数が前記第1の熱膨張係数より大きくなるガラスクロス入りのプリプレグと、第2の銅箔とを準備する工程と、前記片面銅張板の第2の片面に前記プリプレグと前記第2の銅箔とを順次重ねるとともに前記プリプレグを熱硬化させ、前記第1のガラスクロス入り絶縁樹脂層と前記プリプレグの硬化体である第2のガラスクロス入り絶縁樹脂層とが積層一体化された絶縁板の両面に前記第1の銅箔と第2の銅箔とが張り付けられた両面銅張板を形成する工程と、前記両面銅張板の前記第1の銅箔および第2の銅箔を所定パターンにエッチングして前記絶縁板の両面に配線導体が形成されたコア基板を形成する工程と、前記コア基板の片面または両面に、前記第1の熱膨張係数よりも大きな熱膨張係数を有する絶縁樹脂層と導体層とから成るビルドアップ層を、前記第1のガラスクロス入り絶縁樹脂層側で層数が多くなるように積層する工程と、を行うことを特徴とする配線基板の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013039725A JP2014168007A (ja) | 2013-02-28 | 2013-02-28 | 配線基板およびその製造方法 |
TW103106008A TW201448682A (zh) | 2013-02-28 | 2014-02-24 | 配線基板及其製造方法 |
KR1020140023579A KR20140108164A (ko) | 2013-02-28 | 2014-02-27 | 배선 기판 및 그 제조 방법 |
US14/194,067 US20140318834A1 (en) | 2013-02-28 | 2014-05-06 | Wiring board and method for manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013039725A JP2014168007A (ja) | 2013-02-28 | 2013-02-28 | 配線基板およびその製造方法 |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2014168007A true JP2014168007A (ja) | 2014-09-11 |
Family
ID=51617562
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2013039725A Pending JP2014168007A (ja) | 2013-02-28 | 2013-02-28 | 配線基板およびその製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US20140318834A1 (ja) |
JP (1) | JP2014168007A (ja) |
KR (1) | KR20140108164A (ja) |
TW (1) | TW201448682A (ja) |
Cited By (4)
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KR101645478B1 (ko) * | 2015-08-06 | 2016-08-16 | 두두테크 주식회사 | 블루투스용 다층 인쇄회로기판의 제조 방법 |
WO2018043184A1 (ja) * | 2016-08-31 | 2018-03-08 | 大日本印刷株式会社 | 貫通電極基板、貫通電極基板の製造方法及び実装基板 |
CN111148344A (zh) * | 2018-11-05 | 2020-05-12 | 株式会社迪思科 | 布线基板的制造方法 |
JP7428837B2 (ja) | 2022-03-01 | 2024-02-06 | ズハイ アクセス セミコンダクター シーオー.,エルティーディー | パッケージ基板を製造するための載置板、パッケージ基板構造及びその製造方法 |
Families Citing this family (2)
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US10170403B2 (en) * | 2014-12-17 | 2019-01-01 | Kinsus Interconnect Technology Corp. | Ameliorated compound carrier board structure of flip-chip chip-scale package |
US20180122749A1 (en) * | 2016-11-01 | 2018-05-03 | Advanced Semiconductor Engineering, Inc. | Semiconductor wafer, semiconductor package and method for manufacturing the same |
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JP2004095854A (ja) * | 2002-08-30 | 2004-03-25 | Ngk Spark Plug Co Ltd | 多層配線基板 |
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2013
- 2013-02-28 JP JP2013039725A patent/JP2014168007A/ja active Pending
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2014
- 2014-02-24 TW TW103106008A patent/TW201448682A/zh unknown
- 2014-02-27 KR KR1020140023579A patent/KR20140108164A/ko not_active Application Discontinuation
- 2014-05-06 US US14/194,067 patent/US20140318834A1/en not_active Abandoned
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JP2010194930A (ja) * | 2009-02-26 | 2010-09-09 | Sumitomo Bakelite Co Ltd | 絶縁層付支持材料の製造方法、絶縁層付支持材料、プリント配線板および絶縁層付支持材料の製造装置 |
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Cited By (14)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2018513568A (ja) * | 2015-08-06 | 2018-05-24 | ドゥドゥ テック カンパニー リミテッドDodo Tech Co.,Ltd. | ブルートゥース用多層印刷回路基板の製造方法 |
WO2017023098A1 (ko) * | 2015-08-06 | 2017-02-09 | 두두테크 주식회사 | 블루투스용 다층 인쇄회로기판의 제조 방법 |
KR101645478B1 (ko) * | 2015-08-06 | 2016-08-16 | 두두테크 주식회사 | 블루투스용 다층 인쇄회로기판의 제조 방법 |
US11373906B2 (en) | 2016-08-31 | 2022-06-28 | Dai Nippon Printing Co., Ltd. | Through electrode substrate, method of manufacturing through electrode substrate, and mounting substrate |
JPWO2018043184A1 (ja) * | 2016-08-31 | 2019-06-24 | 大日本印刷株式会社 | 貫通電極基板、貫通電極基板の製造方法及び実装基板 |
US10957592B2 (en) | 2016-08-31 | 2021-03-23 | Dai Nippon Printing Co., Ltd. | Through electrode substrate, method of manufacturing through electrode substrate, and mounting substrate |
JP7075625B2 (ja) | 2016-08-31 | 2022-05-26 | 大日本印刷株式会社 | 貫通電極基板、貫通電極基板の製造方法及び実装基板 |
WO2018043184A1 (ja) * | 2016-08-31 | 2018-03-08 | 大日本印刷株式会社 | 貫通電極基板、貫通電極基板の製造方法及び実装基板 |
JP2022107008A (ja) * | 2016-08-31 | 2022-07-20 | 大日本印刷株式会社 | 貫通電極基板、貫通電極基板の製造方法及び実装基板 |
US11810820B2 (en) | 2016-08-31 | 2023-11-07 | Dai Nippon Printing Co., Ltd. | Through electrode substrate, method of manufacturing through electrode substrate, and mounting substrate |
JP7400873B2 (ja) | 2016-08-31 | 2023-12-19 | 大日本印刷株式会社 | 貫通電極基板、貫通電極基板の製造方法及び実装基板 |
CN111148344A (zh) * | 2018-11-05 | 2020-05-12 | 株式会社迪思科 | 布线基板的制造方法 |
JP2020077670A (ja) * | 2018-11-05 | 2020-05-21 | 株式会社ディスコ | 配線基板の製造方法 |
JP7428837B2 (ja) | 2022-03-01 | 2024-02-06 | ズハイ アクセス セミコンダクター シーオー.,エルティーディー | パッケージ基板を製造するための載置板、パッケージ基板構造及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
TW201448682A (zh) | 2014-12-16 |
US20140318834A1 (en) | 2014-10-30 |
KR20140108164A (ko) | 2014-09-05 |
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